Commit Graph

919 Commits

Author SHA1 Message Date
mio
83ad137ac2 Sync HOOK_INSN hooks 2025-04-12 23:22:04 +08:00
mio
4a13bc7cb8 Sync pc before memory hooks
This ensures correct PC for any arch
2025-04-12 22:08:44 +08:00
Amaan Qureshi
3a7bde03b8 feat(arm): add an ESR register (#2155)
This allows users to read/write from the ARM syndrome value like in
AArch64.
2025-04-12 21:46:37 +08:00
mio
7f48b1dd4a No longer used hacked liveness_pass_1
This hack was introduced in issue#287 which later becomes endless maintainance pain.

=====

Our previous check_exit_request use `brcond` in the middle of a TranslationBlock which

breaks the assumptions and thus a hack to liveness_pass_1 is used for _all_ brcond instructions

which causes issues for MIPS and many other scenarios.

=====

This patch also resolves PC not sync-ed when no memory hooks are installed, finally. Now

Unicorn will always have correct PC no matter what happens.
2025-04-12 21:38:14 +08:00
ExhoAR22
bc73cb232d Fix physical address truncation on 32-bit systems with addressing extensions (#2139)
* use hwaddr for paddrs

* Fix the truncation for memory hooks as well

* Add LPAE regression test


Co-authored-by: Takacs, Philipp <philipp.takacs@iosb.fraunhofer.de>
2025-04-01 10:53:18 +08:00
mio
0bb1bbd93c Initialize delay_slot_flag correctly 2025-03-18 21:20:54 +08:00
mio
3870cdcaf3 Format code 2025-03-10 11:31:53 +08:00
mio
d3674f84b4 implement m68k cr registers 2025-03-10 11:31:22 +08:00
PhilippTakacs
65ed715081 Snapshot use after free (#2125)
* memory snapshots fix use after free on flatview copy

When restoring a snapshot with memory the flatview must be restored
before the memory reagions are filtered. Because the
AddressSpaceDispatcher also has pointer to the MemoryRegions and on copy
they need to be cleared. The memory_filter_subregions function frees
MemoryRegions which are not used at the time of the snapshot.

* fix some memleaks in tests

These tests has forgott to call uc_close(uc), which lead to memory
leaks. Found by the LeakSanitizer.

* memory snapshots correct clean up container memory regions

* Fix further stackoverflow in tests

---------

Co-authored-by: mio <mio@lazym.io>
2025-03-06 23:23:02 +08:00
mio
986f67c70a Correct PRI 2025-03-05 00:32:10 +08:00
mio
9da2fec784 Fix mips64 crash on x86 targets 2025-03-04 23:36:56 +08:00
mio
2128e01efc Init tcg region buffer 2025-02-25 13:52:26 +08:00
OBarronCS
76d97f8926 Support MIPS64 - write correct PC register width on uc_emu_start (#2111)
* Support mips64 - write correct pc register width on uc_emu_start

* Convert to UC_MODE_MIPS64

* Correctly select MIPS64 CPU model

* Simple 64-bit test - check it doesn't crash

* lint

* Comment

* Comment

* Add offset when indexing cpu model, makes tests work on older python

* Move test

* add PC check to test

* Fix test - add python version check

* Use RegressTest method for assert
2025-02-21 21:39:11 +08:00
mio
56ba3476e5 Fix long-standing mips delay slot issue 2025-02-19 17:39:24 +08:00
mio
e7ad2fda91 Further fix MIPS delay slot 2025-02-18 23:34:09 +08:00
mio
1cb8952b14 Default x86 CPU model to UC_CPU_X86_HASWELL
Rationale: Previouly, Unicorn uses several hacks to pretend it supports
floating point instructions while not properly setting up something
like CPU features. Therefore, once related registers like CR4 is reset,
the hacks stop working and UC_ERR_INSN_INVALID is thrown. Setting the default
model to a CPu that has basical floating point support should have the
minimal break changes.
2025-02-18 12:13:24 +08:00
mio
4d173ea376 Revert FPU related changes 2025-02-18 11:13:22 +08:00
mio
0f6ec4ca9d Also initialize CR4 for UC_MODE_32 2025-02-18 10:47:35 +08:00
mio
1dae6bb774 Correctly implement CR4 2025-02-18 10:43:52 +08:00
mio
c97449869d Format code 2025-02-17 20:17:10 +08:00
mio
0c6f7c60d5 Implement mips floating point related registers 2025-02-17 20:16:36 +08:00
Disconnect3d
d03c0922e6 Fix #2103: qemu/target/ppc/mem_helper.c remove redundant return statements (#2104) 2025-02-15 01:04:30 +08:00
Amaan Qureshi
6b9c1c851c fix(arm): correct write to ARM coprocessor (#2099)
This code was commented out since 2021, but by default, the error
codewas initialized to `UC_REG_OK`, so there was no error returned
untila result, any write to `UC_ARM_REG_C1_C0_2` returned an error.
2025-02-13 19:25:26 +08:00
mio
791557e404 CI(full),CI(release): Should use if instead of ifdef 2025-02-11 17:44:24 +08:00
mio
5981f10c5d CI(full),CI(release): Fix symbol clash (again) 2025-02-11 16:33:40 +08:00
mio
d437090bbc CI(full),CI(release): Fix symbol clash 2025-02-11 16:28:45 +08:00
mio
b4eb933ec8 CI(full),CI(release): Do not refer to ATOMIC128 symbols if not available 2025-02-11 16:24:49 +08:00
mio
381850356f CI(full),CI(release): More PPC64 atomic fixes 2025-02-11 10:18:01 +08:00
mio
ad33384cd2 Unsigned extension 2025-02-10 21:49:38 +08:00
mio
ca3912d9f7 Fix undefined behavior converting TCGv_i32 to TCGv_i64 2025-02-10 21:45:34 +08:00
mio
c915d13cce Fix pc issue of tcg opcode hooks 2025-02-10 21:35:17 +08:00
mio
77a841e53d Fix signature 2025-02-10 21:29:03 +08:00
mio
2619b12cf0 set pc_start on disasm 2025-02-10 21:28:23 +08:00
mio
904efc16c0 Should use tcg_ctx->pc_start as pc 2025-02-10 21:20:39 +08:00
mio
a903fa182b Avoid null ptr deref when writing to arm context pc register 2025-02-10 15:58:28 +08:00
dotcirill
dc1f7a88d5 Uc hook tcg improve (#2011)
* Add handling UC_TCG_OP_FLAG_CMP for ARM

Implementation is not well-tested and complete

* Hook ARM32 CMP and CMN for cmplog
2025-02-10 15:01:21 +08:00
Shivam7-1
ada8091ccc Fix heap buffer overflow in op_cksm function (#2096)
* Fix heap-buffer-overflow in op_cksm function

* Update header
2025-02-10 14:57:08 +08:00
xndcn
1ba25def8e Fix UC_HOOK_MEM on arm32 (#2091) 2025-01-26 13:28:24 +08:00
ZakDanger
d7c0497ee3 Added start in mips16 mode support, and unit test for it - on dev branch (#2089)
Co-authored-by: ZakDanger <ZakDanger@users.noreply.github.com>
2025-01-19 17:35:40 +08:00
0c512f91a1 Fix #1643
This adds an extra op to translator to allow the block hook sync pc in the very begining
2025-01-18 15:07:22 +08:00
Z. Liu
a78d690da5 configure: add <sys/timex.h> for clock_adjtime on musl (#2085)
for glibc, if _GNU_SOURCE is defined, <time.h> will include <sys/timex.h>
but not for musl, so add "#include <sys/timex.h>"

although `man clock_adjtime` said "#include <sys/timex.h>", but it won't
work for glibc w/o "#include <time.h>", I don't known why yet.

PS it seems clock_adjtime is used nowhere?

Signed-off-by: Z. Liu <zhixu.liu@gmail.com>
2025-01-14 08:47:54 +08:00
Glenn Baker
8442eb6feb qemu/tcg: fix UC_HOOK_MEM_READ on aarch64. (#2028)
* qemu/tcg: fix UC_HOOK_MEM_READ on aarch64.

Directly jump into the slow path when there is any hookmem enabled. This
fixes #1908.

Signed-off-by: Glenn Baker <glenn.baker@gmx.com>

* qemu/tcg: fix UC_HOOK_MEM_READ on ppc64.

Directly jump into the slow path when there is any hookmem enabled.

Signed-off-by: Glenn Baker <glenn.baker@gmx.com>

* qemu/tcg: check for UC_HOOK_MEM_READ_AFTER.

Use has_hookmem() helper to determine wether "slow-path" TLB read is
needed. Add this helper to x86 architecture as well so that to check for
all hookmem.

Signed-off-by: Glenn Baker <glenn.baker@gmx.com>

* qemu/tcg: factor out has_hookmem().

It's the same implementation for all architectures, so factor out
has_hookmem() into tcg_uc_has_hookmem().

Signed-off-by: Glenn Baker <glenn.baker@gmx.com>

---------

Signed-off-by: Glenn Baker <glenn.baker@gmx.com>
2025-01-04 18:48:53 +08:00
mio
2c688bae73 Remove the outdated hack to zero all code gen buffer
This shall also improve performance

Fix #2001
2025-01-04 17:05:34 +08:00
EvianZhang
e97d084aec Add more EIP syncs for x86 target memory hooks (#2064)
Co-authored-by: lazymio <mio@lazym.io>
2025-01-04 15:59:20 +08:00
mio
6974b53588 Fix #2078
We shall only go through the else branch for code_read
2025-01-04 15:57:02 +08:00
mio
fcca82bb28 Format code 2025-01-04 15:48:54 +08:00
Michael-c0de
4f417c3f11 patch multiple UC_HOOK_MEM callbacks for unaligned access (#2063)
* patch multiple UC_HOOK_MEM callbacks for unaligned access

* update test_x86.c for #2063

* update test_x86.c for build on win

---------

Co-authored-by: yaojiale2024@iscas.ac.cn <yaojiale2024@iscas.ac.cn>
Co-authored-by: lazymio <mio@lazym.io>
2024-12-29 23:24:32 +08:00
Pedro Tôrres
7737e7b436 make i386 instructions RDTSC and RDTSCP hookable (#2066)
* instruction hooks for RDTSC and RDTSCP

Signed-off-by: Pedro Tôrres <t0rr3sp3dr0@gmail.com>

* update hookable instruction list

Signed-off-by: Pedro Tôrres <t0rr3sp3dr0@gmail.com>

* test RDTSC and RDTSCP instruction hooks

Signed-off-by: Pedro Tôrres <t0rr3sp3dr0@gmail.com>

---------

Signed-off-by: Pedro Tôrres <t0rr3sp3dr0@gmail.com>
Co-authored-by: mio <mio@lazym.io>
2024-12-20 17:17:23 +08:00
mio
1cbb7b40b2 Allow have_pthread_jit_protect but not have_sprr_mrs 2024-12-20 01:04:50 +08:00
mio
a540df45a6 Only enable SPRR on physical machines 2024-12-20 00:57:19 +08:00