Fix long-standing mips delay slot issue
This commit is contained in:
@@ -41,14 +41,25 @@ static inline void gen_tb_start(TCGContext *tcg_ctx, TranslationBlock *tb)
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tcg_gen_ld_i32(tcg_ctx, count, tcg_ctx->cpu_env,
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offsetof(ArchCPU, neg.icount_decr.u32) -
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offsetof(ArchCPU, env));
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// Unicorn:
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// We CANT'T use brcondi_i32 here or we will fail liveness analysis
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// because it marks the end of BB
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if (tcg_ctx->delay_slot_flag != NULL) {
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TCGv_i32 tmp = tcg_const_i32(tcg_ctx, 0);
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// dest = (c1 cond c2 ? v1 : v2)
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tcg_gen_movcond_i32(tcg_ctx, TCG_COND_GT, count, tcg_ctx->delay_slot_flag, tmp, tcg_ctx->delay_slot_flag, count);
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tcg_temp_free_i32(tcg_ctx, tmp);
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}
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tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_LT, count, 0, tcg_ctx->exitreq_label);
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tcg_temp_free_i32(tcg_ctx, count);
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}
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static inline void gen_tb_end(TCGContext *tcg_ctx, TranslationBlock *tb, int num_insns)
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{
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if (tcg_ctx->delay_slot_flag != NULL){
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tcg_temp_free_i32(tcg_ctx, tcg_ctx->delay_slot_flag);
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}
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tcg_ctx->delay_slot_flag = NULL;
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if (tb_cflags(tb) & CF_USE_ICOUNT) {
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/* Update the num_insn immediate parameter now that we know
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* the actual insn count. */
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@@ -664,6 +664,7 @@ struct TCGContext {
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struct TCGLabelPoolData *pool_labels;
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#endif
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TCGv_i32 delay_slot_flag;
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TCGLabel *exitreq_label;
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TCGTempSet free_temps[TCG_TYPE_COUNT * 2];
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@@ -6006,6 +6006,10 @@ static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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if (use_goto_tb(ctx, dest)) {
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// Unicorn: Force save pc for delay slot instructions, this should be
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// harmless either goto_tb is taken or not but will give correct
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// pc after execution stops within the delay slot.
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gen_save_pc(tcg_ctx, dest);
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tcg_gen_goto_tb(tcg_ctx, n);
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gen_save_pc(tcg_ctx, dest);
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tcg_gen_exit_tb(tcg_ctx, ctx->base.tb, n);
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@@ -30888,6 +30892,9 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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static void mips_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)
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{
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DisasContext *ctx = container_of(dcbase, DisasContext, base);
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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tcg_ctx->delay_slot_flag = tcg_temp_local_new_i32(tcg_ctx);
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}
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static void mips_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
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@@ -30897,6 +30904,7 @@ static void mips_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
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tcg_gen_insn_start(tcg_ctx, ctx->base.pc_next, ctx->hflags & MIPS_HFLAG_BMASK,
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ctx->btarget);
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tcg_gen_movi_i32(tcg_ctx, tcg_ctx->delay_slot_flag, 0);
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}
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static bool mips_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
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@@ -30928,6 +30936,7 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
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int insn_bytes;
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int is_slot;
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bool hook_insn = false;
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TCGv_i32 dyn_is_slot = NULL;
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is_slot = ctx->hflags & MIPS_HFLAG_BMASK;
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@@ -30939,6 +30948,10 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
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return;
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}
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dyn_is_slot = tcg_const_i32(tcg_ctx, 0);
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slot_op = tcg_last_op(tcg_ctx);
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tcg_gen_mov_i32(tcg_ctx, tcg_ctx->delay_slot_flag, dyn_is_slot);
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// Unicorn: trace this instruction on request
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if (HOOK_EXISTS_BOUNDED(uc, UC_HOOK_CODE, ctx->base.pc_next)) {
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@@ -30949,17 +30962,7 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
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prev_op = tcg_last_op(tcg_ctx);
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hook_insn = true;
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gen_uc_tracecode(tcg_ctx, 4, UC_HOOK_CODE_IDX, uc, ctx->base.pc_next);
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// TODO: Memory hooks, maybe use icount_decr.low?
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TCGLabel *skip_label = gen_new_label(tcg_ctx);
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TCGv_i32 dyn_is_slot = tcg_const_i32(tcg_ctx, 0);
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slot_op = tcg_last_op(tcg_ctx);
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// if slot, skip exit_request
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// tcg is smart enough to optimize this branch away
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tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_GT, dyn_is_slot, 0, skip_label);
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tcg_temp_free_i32(tcg_ctx, dyn_is_slot);
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check_exit_request(tcg_ctx);
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gen_set_label(tcg_ctx, skip_label);
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}
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if (ctx->insn_flags & ISA_NANOMIPS32) {
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@@ -30978,6 +30981,7 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
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} else {
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generate_exception_end(ctx, EXCP_RI);
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g_assert(ctx->base.is_jmp == DISAS_NORETURN);
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slot_op->args[1] = is_slot;
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return;
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}
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@@ -31072,6 +31076,10 @@ static void mips_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
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g_assert_not_reached();
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}
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}
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if (tcg_ctx->delay_slot_flag) {
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tcg_temp_free_i32(tcg_ctx, tcg_ctx->delay_slot_flag);
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}
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tcg_ctx->delay_slot_flag = NULL;
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}
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static void mips_sync_pc(DisasContextBase *db, CPUState *cpu)
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@@ -2866,9 +2866,17 @@ void check_exit_request(TCGContext *tcg_ctx)
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tcg_gen_ld_i32(tcg_ctx, count, tcg_ctx->cpu_env,
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offsetof(ArchCPU, neg.icount_decr.u32) -
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offsetof(ArchCPU, env));
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// Unicorn:
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// We CANT'T use brcondi_i32 here or we will fail liveness analysis
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// because it marks the end of BB
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if (tcg_ctx->delay_slot_flag != NULL) {
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TCGv_i32 tmp = tcg_const_i32(tcg_ctx, 0);
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// dest = (c1 cond c2 ? v1 : v2)
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tcg_gen_movcond_i32(tcg_ctx, TCG_COND_GT, count, tcg_ctx->delay_slot_flag, tmp, tcg_ctx->delay_slot_flag, count);
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tcg_temp_free_i32(tcg_ctx, tmp);
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}
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tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_LT, count, 0, tcg_ctx->exitreq_label);
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tcg_temp_free_i32(tcg_ctx, count);
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}
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