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loongarch-port

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• fb8a4f7507 Fix loongarch-port lazymio 2025-04-14 23:10:26 +08:00
• 596478d791 Fix use_lsx_instructions lazymio 2025-04-14 23:09:01 +08:00
• 0cd8b83f5b Squashed commit of the following: WangLiangpu 2025-04-14 23:05:49 +08:00
• fd1bf224e9 fix(python): catch BaseException in wrappers instead of Exception (#2163) Amaan Qureshi 2025-04-14 01:33:51 -04:00
• acb638c40a Further fix incorrect register size mio 2025-04-14 13:12:26 +08:00
• 81a04e222a Fix incorret register size mio 2025-04-14 13:09:43 +08:00
• ed5d47b338 Fixup cr register on be (s390x) mio 2025-04-14 13:04:20 +08:00
• 59ff63a90d Fix cr3 mio 2025-04-14 12:42:28 +08:00
• b20dc83055 Remove extra printing mio 2025-04-14 12:40:16 +08:00
• 2728d8da4f Fix cr0/cr4 should be uint32_t mio 2025-04-14 12:39:53 +08:00
• 542d2f241f Fixup again mio 2025-04-14 12:14:27 +08:00
• 58f954bf75 Fix x86 mmu test on s390x mio 2025-04-14 12:12:37 +08:00
• cccab0b7af handle riscv32 mio 2025-04-14 11:54:24 +08:00
• b59a081d3b Fix riscv MMU implementation not considering BE mio 2025-04-14 00:46:11 +08:00
• 9fd1cd95b9 Fix riscv test endianess issue mio 2025-04-14 00:28:19 +08:00
• 324397f8d2 Fix wrong pc type mio 2025-04-14 00:03:32 +08:00
• ceae547201 avoid inlining memory read/write on s390x mio 2025-04-13 23:48:42 +08:00
• 57eb941cd9 more fix for endianess mio 2025-04-13 23:26:04 +08:00
• d85a372435 fix several tests due to not properly bswap on s390x mio 2025-04-13 23:24:11 +08:00
• 334e83efd7 fix static variables used in m68k mio 2025-04-13 11:49:05 +08:00
• aa86641e16 fix(m68k): correct SR register read (#2161) Amaan Qureshi 2025-04-12 23:03:08 -04:00
• f0bdeb5a74 feat(rust): improve ARM CP register ergonomics (#2160) Amaan Qureshi 2025-04-12 22:36:24 -04:00
• 1b98fec009 fix(rust): watch all source and header files (#2159) Amaan Qureshi 2025-04-12 22:35:38 -04:00
• bac37d2ed7 ignore pc set from ourselves mio 2025-04-13 01:30:25 +08:00
• b8c9d777f4 Fix decleration mio 2025-04-13 01:15:45 +08:00
• 7795248730 Fix PPC symbol clash mio 2025-04-13 01:13:39 +08:00
• bd5a8c5146 Squashed commit of the following: mio 2025-04-13 00:17:55 +08:00
• b999f507b9 fix load_helper & store_helper for PC sync mio 2025-04-12 23:37:20 +08:00
• 2d04b2a71d more PC sync for HOOK_INSN mio 2025-04-12 23:24:49 +08:00
• c9e6fdc4e8 Add PC tests for IN/CPUID mio 2025-04-12 23:22:31 +08:00
• 83ad137ac2 Sync HOOK_INSN hooks mio 2025-04-12 23:22:04 +08:00
• 015e2f27ff Add a test to check memory hooks pc sync mio 2025-04-12 22:52:24 +08:00
• 4a13bc7cb8 Sync pc before memory hooks mio 2025-04-12 22:08:29 +08:00
• 3a7bde03b8 feat(arm): add an ESR register (#2155) Amaan Qureshi 2025-04-12 09:46:37 -04:00
• 7f48b1dd4a No longer used hacked liveness_pass_1 mio 2025-04-12 21:38:14 +08:00
• e89eb87d04 Fixup comments mio 2025-04-11 11:59:00 +08:00
• 9ec0f7558f Add unit tests for mips mio 2025-04-11 11:58:42 +08:00
• e376f98224 Flush tb in uc_close mio 2025-04-11 11:50:10 +08:00
• 143b352775 bindings: ruby: fix version identifier to 2.1.3 (#2142) Levente Polyak 2025-04-05 16:17:04 +02:00
• 1aad423fe5 bindings: ruby: fix unexpected uc_query result pointer type (#1962) Levente Polyak 2025-04-05 00:05:43 +02:00
• f59d5aa4bc refactor(lib): mark pointers as const where possible (#2140) Amaan Qureshi 2025-04-02 10:38:40 -04:00
• bc73cb232d Fix physical address truncation on 32-bit systems with addressing extensions (#2139) ExhoAR22 2025-04-01 05:53:18 +03:00
• 820a18bb90 Fix val mio 2025-03-21 00:36:42 +08:00
• 11a280cdbe Fix naming mio 2025-03-20 16:55:34 +08:00
• 8afc23a839 Add TcgOp mio 2025-03-20 16:54:09 +08:00
• a09b822d8c Add TcgOpFlag mio 2025-03-20 16:51:54 +08:00
• 1aa3909c78 Fix several consts mio 2025-03-20 16:43:03 +08:00
• 0bb1bbd93c Initialize delay_slot_flag correctly mio 2025-03-18 21:20:37 +08:00
• d755a8bed9 bindings/zig: Fix sample_riscv_zig partial writes and logging (#2133) Fernando 2025-03-16 04:05:17 +01:00
• df75effba3 Generate m68k consts mio 2025-03-10 11:32:14 +08:00
• 3870cdcaf3 Format code mio 2025-03-10 11:31:53 +08:00
• d3674f84b4 implement m68k cr registers mio 2025-03-10 11:31:22 +08:00
• 64c72267ae No version suffix for dotnet mio 2025-03-07 22:37:36 +08:00
• 803fe5a477 Update changelog for 2.1.3 mio 2025-03-07 19:43:00 +08:00
• 98f78331ee CI(full), CI(release): Remove pinning Antelox 2025-03-07 11:40:43 +01:00
• d16289fb85 CI(full),CI(release): Last minor changes mio 2025-03-07 17:51:34 +08:00
• 87df11e0c4 Add Alpine Linux job (#2115) @Antelox 2025-03-06 17:42:05 +01:00
• 65ed715081 Snapshot use after free (#2125) PhilippTakacs 2025-03-06 16:23:02 +01:00
• 088c066c59 Remove hack to copy function body mio 2025-03-05 16:49:25 +08:00
• 4dc5f1e60f Fix wrong def mio 2025-03-05 15:16:29 +08:00
• 986f67c70a Correct PRI mio 2025-03-05 00:19:25 +08:00
• e41ccc38e9 bump version mio 2025-03-05 00:18:56 +08:00
• 6335755739 Remove endian.h mio 2025-03-05 00:18:24 +08:00
• f18381016f Python bindings: Port pkg_resources to importlib_resources for python < 3.9 (#2123) @Antelox 2025-03-04 16:55:56 +01:00
• 9da2fec784 Fix mips64 crash on x86 targets mio 2025-03-04 23:36:56 +08:00
• 2128e01efc Init tcg region buffer mio 2025-02-25 13:52:26 +08:00
• 76d97f8926 Support MIPS64 - write correct PC register width on uc_emu_start (#2111) OBarronCS 2025-02-21 05:39:11 -08:00
• 56ba3476e5 Fix long-standing mips delay slot issue mio 2025-02-19 17:39:24 +08:00
• 8a2846369c A real world mips test from Qiling mio 2025-02-19 00:02:19 +08:00
• e7ad2fda91 Further fix MIPS delay slot mio 2025-02-18 23:33:51 +08:00
• 0f45f15e30 Python bindings: (#2112) @Antelox 2025-02-18 09:28:06 +01:00
• 1cb8952b14 Default x86 CPU model to UC_CPU_X86_HASWELL mio 2025-02-18 12:13:24 +08:00
• 4d173ea376 Revert FPU related changes mio 2025-02-18 11:13:22 +08:00
• 795d7cbdf0 Fix testing mio 2025-02-18 11:03:21 +08:00
• 0f6ec4ca9d Also initialize CR4 for UC_MODE_32 mio 2025-02-18 10:47:35 +08:00
• 1dae6bb774 Correctly implement CR4 mio 2025-02-18 10:43:52 +08:00
• 8dcaa33c66 Bump 2.1.3 mio 2025-02-17 20:26:31 +08:00
• 9ec6b0be94 Add a test for fpr mio 2025-02-17 20:23:50 +08:00
• c97449869d Format code mio 2025-02-17 20:17:10 +08:00
• 0c6f7c60d5 Implement mips floating point related registers mio 2025-02-17 20:16:36 +08:00
• f2e80ff5be - Remove a slash for aarch64 job that resulted to be a leftover from previous refactoring (#2107) @Antelox 2025-02-17 04:11:40 +01:00
• 8d52ece48b Replaced custom deprecated decorator with simple DeprecationWarning (#2110) @Antelox 2025-02-16 16:04:42 +01:00
• bf5e335269 Remove types for __deprecated as ParamSpec not available on Py3.8 mio 2025-02-15 20:50:20 +08:00
• 7ec987e626 Basic test for previous regression mio 2025-02-15 20:17:18 +08:00
• a2d666c8e7 Remove incorrect typing reference mio 2025-02-15 20:12:48 +08:00
• a4d8c302a6 Format by removing extra empty lines mio 2025-02-15 20:11:55 +08:00
• c529d6d8f5 We accidentally introduce a break change for mio 2025-02-15 20:04:53 +08:00
• fe41e72b96 GitHub Workflow: (#2106) @Antelox 2025-02-15 11:23:10 +01:00
• d03c0922e6 Fix #2103: qemu/target/ppc/mem_helper.c remove redundant return statements (#2104) Disconnect3d 2025-02-14 18:04:30 +01:00
• 7fd2aa47d4 Fix nuget workflow yaml mio 2025-02-13 23:42:21 +08:00
• 3e99b859a8 Update nuget workflow to allow manual release mio 2025-02-13 23:39:45 +08:00
• a912fed662 CI(release): Update changelog mio 2025-02-13 22:23:08 +08:00
• e2915c978a CI(release): Fix mio 2025-02-13 22:21:25 +08:00
• 0943d24c5f CI(release): ChangeLog mio 2025-02-13 22:20:58 +08:00
• 68ec2d152f CI(release): Trigger CI mio 2025-02-13 21:20:38 +08:00
• cd1492d819 CI(release): Update docs mio 2025-02-13 21:17:29 +08:00
• 1ea6b07653 Update nuget workflow events mio 2025-02-13 21:05:23 +08:00
• 4caee59e8e Skip arm64 macos wheels mio 2025-02-13 20:42:58 +08:00
• 2d410535f0 manually trigger release draft workflows mio 2025-02-13 19:43:47 +08:00
• 6b9c1c851c fix(arm): correct write to ARM coprocessor (#2099) Amaan Qureshi 2025-02-13 06:25:26 -05:00