Generate m68k consts

This commit is contained in:
mio
2025-03-10 11:32:14 +08:00
parent 3870cdcaf3
commit df75effba3
7 changed files with 112 additions and 7 deletions

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@@ -41,5 +41,20 @@ module M68k =
let UC_M68K_REG_D7 = 16
let UC_M68K_REG_SR = 17
let UC_M68K_REG_PC = 18
let UC_M68K_REG_ENDING = 19
let UC_M68K_REG_CR_SFC = 19
let UC_M68K_REG_CR_DFC = 20
let UC_M68K_REG_CR_VBR = 21
let UC_M68K_REG_CR_CACR = 22
let UC_M68K_REG_CR_TC = 23
let UC_M68K_REG_CR_MMUSR = 24
let UC_M68K_REG_CR_SRP = 25
let UC_M68K_REG_CR_USP = 26
let UC_M68K_REG_CR_MSP = 27
let UC_M68K_REG_CR_ISP = 28
let UC_M68K_REG_CR_URP = 29
let UC_M68K_REG_CR_ITT0 = 30
let UC_M68K_REG_CR_ITT1 = 31
let UC_M68K_REG_CR_DTT0 = 32
let UC_M68K_REG_CR_DTT1 = 33
let UC_M68K_REG_ENDING = 34

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@@ -36,5 +36,20 @@ const (
M68K_REG_D7 = 16
M68K_REG_SR = 17
M68K_REG_PC = 18
M68K_REG_ENDING = 19
M68K_REG_CR_SFC = 19
M68K_REG_CR_DFC = 20
M68K_REG_CR_VBR = 21
M68K_REG_CR_CACR = 22
M68K_REG_CR_TC = 23
M68K_REG_CR_MMUSR = 24
M68K_REG_CR_SRP = 25
M68K_REG_CR_USP = 26
M68K_REG_CR_MSP = 27
M68K_REG_CR_ISP = 28
M68K_REG_CR_URP = 29
M68K_REG_CR_ITT0 = 30
M68K_REG_CR_ITT1 = 31
M68K_REG_CR_DTT0 = 32
M68K_REG_CR_DTT1 = 33
M68K_REG_ENDING = 34
)

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@@ -38,6 +38,21 @@ public interface M68kConst {
public static final int UC_M68K_REG_D7 = 16;
public static final int UC_M68K_REG_SR = 17;
public static final int UC_M68K_REG_PC = 18;
public static final int UC_M68K_REG_ENDING = 19;
public static final int UC_M68K_REG_CR_SFC = 19;
public static final int UC_M68K_REG_CR_DFC = 20;
public static final int UC_M68K_REG_CR_VBR = 21;
public static final int UC_M68K_REG_CR_CACR = 22;
public static final int UC_M68K_REG_CR_TC = 23;
public static final int UC_M68K_REG_CR_MMUSR = 24;
public static final int UC_M68K_REG_CR_SRP = 25;
public static final int UC_M68K_REG_CR_USP = 26;
public static final int UC_M68K_REG_CR_MSP = 27;
public static final int UC_M68K_REG_CR_ISP = 28;
public static final int UC_M68K_REG_CR_URP = 29;
public static final int UC_M68K_REG_CR_ITT0 = 30;
public static final int UC_M68K_REG_CR_ITT1 = 31;
public static final int UC_M68K_REG_CR_DTT0 = 32;
public static final int UC_M68K_REG_CR_DTT1 = 33;
public static final int UC_M68K_REG_ENDING = 34;
}

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@@ -39,7 +39,22 @@ const
UC_M68K_REG_D7 = 16;
UC_M68K_REG_SR = 17;
UC_M68K_REG_PC = 18;
UC_M68K_REG_ENDING = 19;
UC_M68K_REG_CR_SFC = 19;
UC_M68K_REG_CR_DFC = 20;
UC_M68K_REG_CR_VBR = 21;
UC_M68K_REG_CR_CACR = 22;
UC_M68K_REG_CR_TC = 23;
UC_M68K_REG_CR_MMUSR = 24;
UC_M68K_REG_CR_SRP = 25;
UC_M68K_REG_CR_USP = 26;
UC_M68K_REG_CR_MSP = 27;
UC_M68K_REG_CR_ISP = 28;
UC_M68K_REG_CR_URP = 29;
UC_M68K_REG_CR_ITT0 = 30;
UC_M68K_REG_CR_ITT1 = 31;
UC_M68K_REG_CR_DTT0 = 32;
UC_M68K_REG_CR_DTT1 = 33;
UC_M68K_REG_ENDING = 34;
implementation
end.

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@@ -34,4 +34,19 @@ UC_M68K_REG_D6 = 15
UC_M68K_REG_D7 = 16
UC_M68K_REG_SR = 17
UC_M68K_REG_PC = 18
UC_M68K_REG_ENDING = 19
UC_M68K_REG_CR_SFC = 19
UC_M68K_REG_CR_DFC = 20
UC_M68K_REG_CR_VBR = 21
UC_M68K_REG_CR_CACR = 22
UC_M68K_REG_CR_TC = 23
UC_M68K_REG_CR_MMUSR = 24
UC_M68K_REG_CR_SRP = 25
UC_M68K_REG_CR_USP = 26
UC_M68K_REG_CR_MSP = 27
UC_M68K_REG_CR_ISP = 28
UC_M68K_REG_CR_URP = 29
UC_M68K_REG_CR_ITT0 = 30
UC_M68K_REG_CR_ITT1 = 31
UC_M68K_REG_CR_DTT0 = 32
UC_M68K_REG_CR_DTT1 = 33
UC_M68K_REG_ENDING = 34

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@@ -36,5 +36,20 @@ module UnicornEngine
UC_M68K_REG_D7 = 16
UC_M68K_REG_SR = 17
UC_M68K_REG_PC = 18
UC_M68K_REG_ENDING = 19
UC_M68K_REG_CR_SFC = 19
UC_M68K_REG_CR_DFC = 20
UC_M68K_REG_CR_VBR = 21
UC_M68K_REG_CR_CACR = 22
UC_M68K_REG_CR_TC = 23
UC_M68K_REG_CR_MMUSR = 24
UC_M68K_REG_CR_SRP = 25
UC_M68K_REG_CR_USP = 26
UC_M68K_REG_CR_MSP = 27
UC_M68K_REG_CR_ISP = 28
UC_M68K_REG_CR_URP = 29
UC_M68K_REG_CR_ITT0 = 30
UC_M68K_REG_CR_ITT1 = 31
UC_M68K_REG_CR_DTT0 = 32
UC_M68K_REG_CR_DTT1 = 33
UC_M68K_REG_ENDING = 34
end

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@@ -36,6 +36,21 @@ pub const m68kConst = enum(c_int) {
M68K_REG_D7 = 16,
M68K_REG_SR = 17,
M68K_REG_PC = 18,
M68K_REG_ENDING = 19,
M68K_REG_CR_SFC = 19,
M68K_REG_CR_DFC = 20,
M68K_REG_CR_VBR = 21,
M68K_REG_CR_CACR = 22,
M68K_REG_CR_TC = 23,
M68K_REG_CR_MMUSR = 24,
M68K_REG_CR_SRP = 25,
M68K_REG_CR_USP = 26,
M68K_REG_CR_MSP = 27,
M68K_REG_CR_ISP = 28,
M68K_REG_CR_URP = 29,
M68K_REG_CR_ITT0 = 30,
M68K_REG_CR_ITT1 = 31,
M68K_REG_CR_DTT0 = 32,
M68K_REG_CR_DTT1 = 33,
M68K_REG_ENDING = 34,
};