Fix use_lsx_instructions
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@@ -815,6 +815,9 @@ struct TCGContext {
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char s390x_cpu_reg_names[16][4]; // renamed from original cpu_reg_names[][] to avoid name clash with m68k
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TCGv_i64 regs[16];
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// loongarch
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bool use_lsx_instructions;
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};
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static inline size_t temp_idx(TCGContext *tcg_ctx, TCGTemp *ts)
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@@ -97,8 +97,6 @@ typedef enum {
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TCG_VEC_TMP0 = TCG_REG_V23,
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} TCGReg;
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extern bool use_lsx_instructions;
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/* used for function call generation */
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#define TCG_REG_CALL_STACK TCG_REG_SP
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#define TCG_TARGET_STACK_ALIGN 16
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@@ -187,10 +185,10 @@ extern bool use_lsx_instructions;
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#define TCG_TARGET_HAS_mulsh_i64 1
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#define TCG_TARGET_HAS_direct_jump 0
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#define TCG_TARGET_HAS_qemu_ldst_i128 use_lsx_instructions
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#define TCG_TARGET_HAS_qemu_ldst_i128 s->use_lsx_instructions
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#define TCG_TARGET_HAS_v64 0
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#define TCG_TARGET_HAS_v128 use_lsx_instructions
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#define TCG_TARGET_HAS_v128 s->use_lsx_instructions
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#define TCG_TARGET_HAS_v256 0
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#define TCG_TARGET_HAS_not_vec 1
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@@ -32,8 +32,6 @@
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#include "../tcg-ldst.inc.c"
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#include <asm/hwcap.h>
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bool use_lsx_instructions;
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#ifdef CONFIG_DEBUG_TCG
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static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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"zero",
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@@ -2604,10 +2602,10 @@ static void tcg_target_init(TCGContext *s)
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}
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if (hwcap & HWCAP_LOONGARCH_LSX) {
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use_lsx_instructions = 1;
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s->use_lsx_instructions = 1;
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}
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#else
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use_lsx_instructions = 1;
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s->use_lsx_instructions = 1;
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#endif
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s->tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
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