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feat(arm): add an ESR register (#2155)

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This allows users to read/write from the ARM syndrome value like in
AArch64.
This commit is contained in:
Amaan Qureshi
2025-04-12 09:46:37 -04:00
committed by GitHub
parent 7f48b1dd4a
commit 3a7bde03b8
11 changed files with 73 additions and 16 deletions
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8
qemu/target/arm/unicorn_arm.c
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@@ -352,6 +352,10 @@ uc_err reg_read(void *_env, int mode, unsigned int regid, void *value,
CHECK_REG_TYPE(uc_arm_cp_reg);
ret = read_cp_reg(env, (uc_arm_cp_reg *)value);
break;
case UC_ARM_REG_ESR:
CHECK_REG_TYPE(uint32_t);
*(uint32_t *)value = env->exception.syndrome;
break;
}
}
@@ -556,6 +560,10 @@ uc_err reg_write(void *_env, int mode, unsigned int regid, const void *value,
ret = write_cp_reg(env, (uc_arm_cp_reg *)value);
arm_rebuild_hflags_arm(env);
break;
case UC_ARM_REG_ESR:
CHECK_REG_TYPE(uint32_t);
env->exception.syndrome = *(uint32_t *)value;
break;
}
}