Commit Graph

3294 Commits

Author SHA1 Message Date
fb8a4f7507 Fix
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2025-04-14 23:10:26 +08:00
596478d791 Fix use_lsx_instructions
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2025-04-14 23:09:01 +08:00
WangLiangpu
0cd8b83f5b Squashed commit of the following:
commit 2d9587f26b
Author: WangLiangpu <wangjingpu17@mails.ucas.ac.cn>
Date:   Wed Nov 1 21:36:35 2023 +0800

    fix: fix tcg_out_dupi_vec interface conflicts

commit b957324d3d
Author: zhaodongru <zhaodongru@yeah.net>
Date:   Mon Oct 23 18:15:01 2023 +0800

    start loongarch compile

    fix: modify the code to pass compile

    add: add code for tcg_out_op, tcg_can_emit_vec_op, tcg_target_op_def to support new tcg_op

    fix: fix bugs related to epilogue and ret_addr

    fix: fix bug in qemu_ld_slow_path, the return register is wrong
2025-04-14 23:05:49 +08:00
Amaan Qureshi
fd1bf224e9 fix(python): catch BaseException in wrappers instead of Exception (#2163)
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2025-04-14 13:33:51 +08:00
mio
acb638c40a Further fix incorrect register size 2025-04-14 13:12:26 +08:00
mio
81a04e222a Fix incorret register size 2025-04-14 13:09:43 +08:00
mio
ed5d47b338 Fixup cr register on be (s390x) 2025-04-14 13:04:20 +08:00
mio
59ff63a90d Fix cr3 2025-04-14 12:42:28 +08:00
mio
b20dc83055 Remove extra printing 2025-04-14 12:40:16 +08:00
mio
2728d8da4f Fix cr0/cr4 should be uint32_t 2025-04-14 12:39:53 +08:00
mio
542d2f241f Fixup again 2025-04-14 12:14:27 +08:00
mio
58f954bf75 Fix x86 mmu test on s390x 2025-04-14 12:12:37 +08:00
mio
cccab0b7af handle riscv32 2025-04-14 11:54:24 +08:00
mio
b59a081d3b Fix riscv MMU implementation not considering BE 2025-04-14 00:46:11 +08:00
mio
9fd1cd95b9 Fix riscv test endianess issue 2025-04-14 00:28:19 +08:00
mio
324397f8d2 Fix wrong pc type 2025-04-14 00:03:32 +08:00
mio
ceae547201 avoid inlining memory read/write on s390x 2025-04-13 23:48:42 +08:00
mio
57eb941cd9 more fix for endianess 2025-04-13 23:26:04 +08:00
mio
d85a372435 fix several tests due to not properly bswap on s390x 2025-04-13 23:24:11 +08:00
mio
334e83efd7 fix static variables used in m68k 2025-04-13 11:49:05 +08:00
Amaan Qureshi
aa86641e16 fix(m68k): correct SR register read (#2161)
The SR register in the `CPUM68KState` struct does not contain the value
of the lower 5 flags. To compute them, we must OR the CCR values with
the SR register to get the true SR value.
2025-04-13 11:03:08 +08:00
Amaan Qureshi
f0bdeb5a74 feat(rust): improve ARM CP register ergonomics (#2160) 2025-04-13 10:36:24 +08:00
Amaan Qureshi
1b98fec009 fix(rust): watch all source and header files (#2159)
This will trigger a rebuild when any files change, instead of having to
have to trigger it manually
2025-04-13 10:35:38 +08:00
mio
bac37d2ed7 ignore pc set from ourselves 2025-04-13 01:30:25 +08:00
mio
b8c9d777f4 Fix decleration 2025-04-13 01:15:45 +08:00
mio
7795248730 Fix PPC symbol clash 2025-04-13 01:13:39 +08:00
mio
bd5a8c5146 Squashed commit of the following:
commit 520c6647c32f02d83083d969d416154aa95e922c
Merge: 6bb29b12 b999f507
Author: mio <mio@lazym.io>
Date:   Sun Apr 13 00:14:23 2025 +0800

    merge dev

commit 6bb29b12f1d9f452365cc9cb5bc2d65ef376af30
Author: mio <mio@lazym.io>
Date:   Sun Apr 13 00:13:12 2025 +0800

    enable test

commit bcb8b363ef12ac295cf4fe4f1645416e5f0ea6ae
Author: mio <mio@lazym.io>
Date:   Sun Apr 13 00:13:06 2025 +0800

    also logging

commit 5972fc156b7379d09582c745d6d597e07555f2f4
Author: mio <mio@lazym.io>
Date:   Sun Apr 13 00:12:58 2025 +0800

    no unlimited translation

commit 7d600feebf9055505918e50d0af8b529a3eba542
Author: mio <mio@lazym.io>
Date:   Sun Apr 13 00:12:47 2025 +0800

    Ignore bindings.rs

commit dde4d50f2c7713156ac3bc284287480e4d92005f
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sun Apr 6 03:26:22 2025 -0400

    alias `uc_mips_reg` to `UC_MIPS_REG`

commit 04234ae01ba7c82d9717eaae64cdda289ce3b832
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sun Apr 6 01:13:00 2025 -0400

    remove bindings.rs

commit edec1300cd7c2d8ef4babbd51f6bcba2e126bdd7
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sat Apr 5 14:29:40 2025 -0400

    address review

commit feb157b28b6c262c5dc3d810ec54de55a25bcd6e
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sat Mar 29 22:40:53 2025 -0400

    ci(rust): rework workflow

    The notable changes are migrating to
    `actions-rust-lang/setup-rust-toolchain` for setting up Rust as it's
    maintained, and using `katyo/publish-crates` for publishing crates in a
    workspace

commit c1c7a8f8ed841b6ec5b4abe57013a1c2c9748c60
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sat Mar 29 22:40:06 2025 -0400

    build(rust): set `rust-version` to 1.85

commit 8df938c9f8b478160213707674157103b0893caf
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sat Mar 29 21:53:21 2025 -0400

    fix(rust): correct unsound pointer cast

    The size of `T` is not guaranteed to be the size of `i32` - all we know
    is that `T` is `Into<i32>`, so we should first copy them over into an
    `i32` array

commit 3059b2583a60aa0cac9278afc945ed87f7ddb65e
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sat Mar 29 20:13:26 2025 -0400

    docs(rust): update readme

commit 7db69a888e58a4bda20083e4e0771d26a327ad13
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sat Mar 29 13:58:30 2025 -0400

    feat(rust): add comprehensive tests

    These tests are copied over from the C tests

commit 78f2207f0e0481aef4de6d5908f8dc699a39a8d5
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sat Mar 29 13:57:27 2025 -0400

    feat(rust): add tcg hook

commit 46e53328531ec3279dadbf18c16b493432227b31
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sat Mar 29 13:56:55 2025 -0400

    feat(rust): add a hook for arm64 sys instructions

commit d1b58ee8282bf1eeeefbf68c87c2cf7c50c90320
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sat Mar 29 13:56:35 2025 -0400

    feat(rust): add the ability to read the arm coprocessor register

commit d304da18b9e6741042b2a70657437be8f39f5c7c
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sat Mar 29 13:55:29 2025 -0400

    feat(rust): add missing `Context` methods

commit 0dd87833081ac9db1feaf5bae8c839a7a2ae4947
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sat Mar 29 13:44:51 2025 -0400

    refactor(rust): remove unnecessary code

    `unicorn-engine-sys` will provide the necessary constants & types

commit da3d2fa7c3ecd3ae8fdb6672b6c5ea23da4570ff
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sat Mar 29 13:43:57 2025 -0400

    feat(rust): add a workspace `Cargo.toml`, and use `unicorn-engine-sys`

commit b27a2a93e4ac43aa2079e936df4dd30a1f8f329a
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sat Mar 29 13:38:06 2025 -0400

    feat(rust): introduce `unicorn-engine-sys` crate

    This crate contains generated Rust bindings to the C library via
    bindgen. It is independent from the main `unicorn-engine` bindings,
    which will leverage this

commit bcec87a3f6e316e328683c303ccfa89e530a6c56
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sat Mar 29 13:31:24 2025 -0400

    test(m68k): actually assert an expectation

    This test did not actually test for anything before

commit bc7e65ca96164496eb2e250b1f296a33a8aa58ee
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sat Mar 29 13:31:09 2025 -0400

    style(test): use bitflag shorthands

commit 0ab4b7fefb3ca17b0b5977d7b204291c5de184ad
Author: Amaan Qureshi <amaanq12@gmail.com>
Date:   Sat Mar 29 13:22:13 2025 -0400

    fix(mips): lowercase enum name `uc_mips_reg`

    This aligns with other architectures

Co-authored-by: Amaan Qureshi <amaanq12@gmail.com>
2025-04-13 00:17:55 +08:00
mio
b999f507b9 fix load_helper & store_helper for PC sync 2025-04-12 23:37:20 +08:00
mio
2d04b2a71d more PC sync for HOOK_INSN 2025-04-12 23:24:49 +08:00
mio
c9e6fdc4e8 Add PC tests for IN/CPUID 2025-04-12 23:22:31 +08:00
mio
83ad137ac2 Sync HOOK_INSN hooks 2025-04-12 23:22:04 +08:00
mio
015e2f27ff Add a test to check memory hooks pc sync 2025-04-12 22:52:24 +08:00
mio
4a13bc7cb8 Sync pc before memory hooks
This ensures correct PC for any arch
2025-04-12 22:08:44 +08:00
Amaan Qureshi
3a7bde03b8 feat(arm): add an ESR register (#2155)
This allows users to read/write from the ARM syndrome value like in
AArch64.
2025-04-12 21:46:37 +08:00
mio
7f48b1dd4a No longer used hacked liveness_pass_1
This hack was introduced in issue#287 which later becomes endless maintainance pain.

=====

Our previous check_exit_request use `brcond` in the middle of a TranslationBlock which

breaks the assumptions and thus a hack to liveness_pass_1 is used for _all_ brcond instructions

which causes issues for MIPS and many other scenarios.

=====

This patch also resolves PC not sync-ed when no memory hooks are installed, finally. Now

Unicorn will always have correct PC no matter what happens.
2025-04-12 21:38:14 +08:00
mio
e89eb87d04 Fixup comments 2025-04-11 11:59:00 +08:00
mio
9ec0f7558f Add unit tests for mips 2025-04-11 11:58:42 +08:00
mio
e376f98224 Flush tb in uc_close 2025-04-11 11:50:10 +08:00
Levente Polyak
143b352775 bindings: ruby: fix version identifier to 2.1.3 (#2142) 2025-04-05 22:17:04 +08:00
Levente Polyak
1aad423fe5 bindings: ruby: fix unexpected uc_query result pointer type (#1962)
uc_query expects a size_t *, while we are passing uc_arch *. This has
been working for a while as gcc just warned about this, however with
latest gcc this changed into an error:

unicorn.c:122:34: error: passing argument 3 of ‘uc_query’ from incompatible pointer type [-Wincompatible-pointer-types]
  206 |     uc_query(_uc, UC_QUERY_ARCH, &arch);
unicorn.h:689:60: note: expected ‘size_t *’ {aka ‘long unsigned int *’} but argument is of type ‘uc_arch *’
  689 | uc_err uc_query(uc_engine *uc, uc_query_type type, size_t *result);

Fix this issue by querying the result into a size_t and later downcast
the result into an uc_arch enum.
2025-04-05 06:05:43 +08:00
Amaan Qureshi
f59d5aa4bc refactor(lib): mark pointers as const where possible (#2140) 2025-04-02 22:38:40 +08:00
ExhoAR22
bc73cb232d Fix physical address truncation on 32-bit systems with addressing extensions (#2139)
* use hwaddr for paddrs

* Fix the truncation for memory hooks as well

* Add LPAE regression test


Co-authored-by: Takacs, Philipp <philipp.takacs@iosb.fraunhofer.de>
2025-04-01 10:53:18 +08:00
mio
820a18bb90 Fix val 2025-03-21 00:36:42 +08:00
mio
11a280cdbe Fix naming 2025-03-20 16:55:34 +08:00
mio
8afc23a839 Add TcgOp 2025-03-20 16:54:09 +08:00
mio
a09b822d8c Add TcgOpFlag 2025-03-20 16:51:54 +08:00
mio
1aa3909c78 Fix several consts
We should bump these for next release
2025-03-20 16:43:03 +08:00
mio
0bb1bbd93c Initialize delay_slot_flag correctly 2025-03-18 21:20:54 +08:00
Fernando
d755a8bed9 bindings/zig: Fix sample_riscv_zig partial writes and logging (#2133)
- Use full code length (instead of subtracting 1) when writing instructions.
- Uniformly zero-pad addresses in logs and print hexadecimal.
- Correct the instruction-hook callback in test_riscv2.
2025-03-16 11:05:17 +08:00
mio
df75effba3 Generate m68k consts 2025-03-10 11:32:14 +08:00