Commit Graph

909 Commits

Author SHA1 Message Date
mio
9da2fec784 Fix mips64 crash on x86 targets 2025-03-04 23:36:56 +08:00
mio
2128e01efc Init tcg region buffer 2025-02-25 13:52:26 +08:00
OBarronCS
76d97f8926 Support MIPS64 - write correct PC register width on uc_emu_start (#2111)
* Support mips64 - write correct pc register width on uc_emu_start

* Convert to UC_MODE_MIPS64

* Correctly select MIPS64 CPU model

* Simple 64-bit test - check it doesn't crash

* lint

* Comment

* Comment

* Add offset when indexing cpu model, makes tests work on older python

* Move test

* add PC check to test

* Fix test - add python version check

* Use RegressTest method for assert
2025-02-21 21:39:11 +08:00
mio
56ba3476e5 Fix long-standing mips delay slot issue 2025-02-19 17:39:24 +08:00
mio
e7ad2fda91 Further fix MIPS delay slot 2025-02-18 23:34:09 +08:00
mio
1cb8952b14 Default x86 CPU model to UC_CPU_X86_HASWELL
Rationale: Previouly, Unicorn uses several hacks to pretend it supports
floating point instructions while not properly setting up something
like CPU features. Therefore, once related registers like CR4 is reset,
the hacks stop working and UC_ERR_INSN_INVALID is thrown. Setting the default
model to a CPu that has basical floating point support should have the
minimal break changes.
2025-02-18 12:13:24 +08:00
mio
4d173ea376 Revert FPU related changes 2025-02-18 11:13:22 +08:00
mio
0f6ec4ca9d Also initialize CR4 for UC_MODE_32 2025-02-18 10:47:35 +08:00
mio
1dae6bb774 Correctly implement CR4 2025-02-18 10:43:52 +08:00
mio
c97449869d Format code 2025-02-17 20:17:10 +08:00
mio
0c6f7c60d5 Implement mips floating point related registers 2025-02-17 20:16:36 +08:00
Disconnect3d
d03c0922e6 Fix #2103: qemu/target/ppc/mem_helper.c remove redundant return statements (#2104) 2025-02-15 01:04:30 +08:00
Amaan Qureshi
6b9c1c851c fix(arm): correct write to ARM coprocessor (#2099)
This code was commented out since 2021, but by default, the error
codewas initialized to `UC_REG_OK`, so there was no error returned
untila result, any write to `UC_ARM_REG_C1_C0_2` returned an error.
2025-02-13 19:25:26 +08:00
mio
791557e404 CI(full),CI(release): Should use if instead of ifdef 2025-02-11 17:44:24 +08:00
mio
5981f10c5d CI(full),CI(release): Fix symbol clash (again) 2025-02-11 16:33:40 +08:00
mio
d437090bbc CI(full),CI(release): Fix symbol clash 2025-02-11 16:28:45 +08:00
mio
b4eb933ec8 CI(full),CI(release): Do not refer to ATOMIC128 symbols if not available 2025-02-11 16:24:49 +08:00
mio
381850356f CI(full),CI(release): More PPC64 atomic fixes 2025-02-11 10:18:01 +08:00
mio
ad33384cd2 Unsigned extension 2025-02-10 21:49:38 +08:00
mio
ca3912d9f7 Fix undefined behavior converting TCGv_i32 to TCGv_i64 2025-02-10 21:45:34 +08:00
mio
c915d13cce Fix pc issue of tcg opcode hooks 2025-02-10 21:35:17 +08:00
mio
77a841e53d Fix signature 2025-02-10 21:29:03 +08:00
mio
2619b12cf0 set pc_start on disasm 2025-02-10 21:28:23 +08:00
mio
904efc16c0 Should use tcg_ctx->pc_start as pc 2025-02-10 21:20:39 +08:00
mio
a903fa182b Avoid null ptr deref when writing to arm context pc register 2025-02-10 15:58:28 +08:00
dotcirill
dc1f7a88d5 Uc hook tcg improve (#2011)
* Add handling UC_TCG_OP_FLAG_CMP for ARM

Implementation is not well-tested and complete

* Hook ARM32 CMP and CMN for cmplog
2025-02-10 15:01:21 +08:00
Shivam7-1
ada8091ccc Fix heap buffer overflow in op_cksm function (#2096)
* Fix heap-buffer-overflow in op_cksm function

* Update header
2025-02-10 14:57:08 +08:00
xndcn
1ba25def8e Fix UC_HOOK_MEM on arm32 (#2091) 2025-01-26 13:28:24 +08:00
ZakDanger
d7c0497ee3 Added start in mips16 mode support, and unit test for it - on dev branch (#2089)
Co-authored-by: ZakDanger <ZakDanger@users.noreply.github.com>
2025-01-19 17:35:40 +08:00
0c512f91a1 Fix #1643
This adds an extra op to translator to allow the block hook sync pc in the very begining
2025-01-18 15:07:22 +08:00
Z. Liu
a78d690da5 configure: add <sys/timex.h> for clock_adjtime on musl (#2085)
for glibc, if _GNU_SOURCE is defined, <time.h> will include <sys/timex.h>
but not for musl, so add "#include <sys/timex.h>"

although `man clock_adjtime` said "#include <sys/timex.h>", but it won't
work for glibc w/o "#include <time.h>", I don't known why yet.

PS it seems clock_adjtime is used nowhere?

Signed-off-by: Z. Liu <zhixu.liu@gmail.com>
2025-01-14 08:47:54 +08:00
Glenn Baker
8442eb6feb qemu/tcg: fix UC_HOOK_MEM_READ on aarch64. (#2028)
* qemu/tcg: fix UC_HOOK_MEM_READ on aarch64.

Directly jump into the slow path when there is any hookmem enabled. This
fixes #1908.

Signed-off-by: Glenn Baker <glenn.baker@gmx.com>

* qemu/tcg: fix UC_HOOK_MEM_READ on ppc64.

Directly jump into the slow path when there is any hookmem enabled.

Signed-off-by: Glenn Baker <glenn.baker@gmx.com>

* qemu/tcg: check for UC_HOOK_MEM_READ_AFTER.

Use has_hookmem() helper to determine wether "slow-path" TLB read is
needed. Add this helper to x86 architecture as well so that to check for
all hookmem.

Signed-off-by: Glenn Baker <glenn.baker@gmx.com>

* qemu/tcg: factor out has_hookmem().

It's the same implementation for all architectures, so factor out
has_hookmem() into tcg_uc_has_hookmem().

Signed-off-by: Glenn Baker <glenn.baker@gmx.com>

---------

Signed-off-by: Glenn Baker <glenn.baker@gmx.com>
2025-01-04 18:48:53 +08:00
mio
2c688bae73 Remove the outdated hack to zero all code gen buffer
This shall also improve performance

Fix #2001
2025-01-04 17:05:34 +08:00
EvianZhang
e97d084aec Add more EIP syncs for x86 target memory hooks (#2064)
Co-authored-by: lazymio <mio@lazym.io>
2025-01-04 15:59:20 +08:00
mio
6974b53588 Fix #2078
We shall only go through the else branch for code_read
2025-01-04 15:57:02 +08:00
mio
fcca82bb28 Format code 2025-01-04 15:48:54 +08:00
Michael-c0de
4f417c3f11 patch multiple UC_HOOK_MEM callbacks for unaligned access (#2063)
* patch multiple UC_HOOK_MEM callbacks for unaligned access

* update test_x86.c for #2063

* update test_x86.c for build on win

---------

Co-authored-by: yaojiale2024@iscas.ac.cn <yaojiale2024@iscas.ac.cn>
Co-authored-by: lazymio <mio@lazym.io>
2024-12-29 23:24:32 +08:00
Pedro Tôrres
7737e7b436 make i386 instructions RDTSC and RDTSCP hookable (#2066)
* instruction hooks for RDTSC and RDTSCP

Signed-off-by: Pedro Tôrres <t0rr3sp3dr0@gmail.com>

* update hookable instruction list

Signed-off-by: Pedro Tôrres <t0rr3sp3dr0@gmail.com>

* test RDTSC and RDTSCP instruction hooks

Signed-off-by: Pedro Tôrres <t0rr3sp3dr0@gmail.com>

---------

Signed-off-by: Pedro Tôrres <t0rr3sp3dr0@gmail.com>
Co-authored-by: mio <mio@lazym.io>
2024-12-20 17:17:23 +08:00
mio
1cbb7b40b2 Allow have_pthread_jit_protect but not have_sprr_mrs 2024-12-20 01:04:50 +08:00
mio
a540df45a6 Only enable SPRR on physical machines 2024-12-20 00:57:19 +08:00
mio
1ad2da35e6 Fix QEMU_UNUSED_FUNC 2024-12-20 00:50:11 +08:00
13a8da8538 Check SPRR by issuing MRS 2024-12-08 14:46:28 +08:00
958ed09153 No longer need SPRR and probe it runtime 2024-12-07 23:33:34 +08:00
b0b412bc6c Only enable JIT protect support with SPRR 2024-12-07 22:35:28 +08:00
69200d4f00 Fix regression: If invalid instruction is handled, allow emulation to continue 2024-12-07 17:30:45 +08:00
3b2f54fc61 Fix regression: We should triage MIPS internal exceptions to Unicorn exceptions 2024-12-07 17:09:59 +08:00
c22651c9fe Fix regression: We should also sync npc for SPARC 2024-12-07 16:31:20 +08:00
9ec1f604dc Fix regression: Setting eflags within the hook should take effect
This add an extra compute_eflags after the hooks
2024-12-07 15:56:56 +08:00
Martin Atkins
7d8fe2ab11 riscv: Expose privilege level as pseudo-register PRIV (#1989)
Unlike some other architectures, RISC-V does not expose the current
privilege mode in any architecturally-defined register. That is intentional
to make it easier to implement virtualization in software, but a Unicorn
caller operates outside of the emulated hart and so it can and should be
able to observe and change the current privilege mode in order to properly
emulate certain behaviors of a real CPU.

The current privilege level is therefore now exposed as a new
pseudo-register using the name "priv", which matches the name of the
virtual register used by RISC-V's debug extension to allow the debugger
to read and change the privilege mode while the hart is halted. Unicorn's
use of it is conceptually similar to a debugger.

The bit encoding of this register is the same as specified in RISC-V Debug
Specification v1.0-rc3 Section 4.10.1. It's defined as a "virtual"
register exposing a subset of fields from the dcsr register, although here
it's implemented directly inside the Unicorn code because QEMU doesn't
currently have explicit support for the CSRs from the debug specification.
If it supports "dcsr" in a future release then this implementation could
change to wrap reading and writing that CSR and then projecting the "prv"
and "v" bitfields into the correct locations for the virtual register.
2024-11-11 21:09:45 +08:00
tbodt
f71bc1a115 Several bugfixes (#2049)
* Remove global variable from aarch64 tcg target

This obviously breaks trying to run two unicorn instances at once on
aarch64. It appears a similar variable had already been moved to the
state struct for i386 tcg target.

* Reenable writing to jit region while calling tb_add_jump

On arm macs, every place that writes to jit code needs to have
tb_exec_unlock called first. This is already in most necessary places,
but not this one.

* Don't forget to call restore_jit_state in uc_context_restore

Every time UC_INIT is used, restore_jit_state must be used on the return
path, or occasional assertion failures will pop up on arm macs.

* Restore pc before calling into tlb fill hook

In my application it is important to have correct pc values available
from this hook.
2024-11-04 12:53:26 +08:00