Commit Graph

536 Commits

Author SHA1 Message Date
OBarronCS
76d97f8926 Support MIPS64 - write correct PC register width on uc_emu_start (#2111)
* Support mips64 - write correct pc register width on uc_emu_start

* Convert to UC_MODE_MIPS64

* Correctly select MIPS64 CPU model

* Simple 64-bit test - check it doesn't crash

* lint

* Comment

* Comment

* Add offset when indexing cpu model, makes tests work on older python

* Move test

* add PC check to test

* Fix test - add python version check

* Use RegressTest method for assert
2025-02-21 21:39:11 +08:00
mio
56ba3476e5 Fix long-standing mips delay slot issue 2025-02-19 17:39:24 +08:00
mio
8a2846369c A real world mips test from Qiling 2025-02-19 00:02:19 +08:00
mio
e7ad2fda91 Further fix MIPS delay slot 2025-02-18 23:34:09 +08:00
mio
795d7cbdf0 Fix testing 2025-02-18 11:03:21 +08:00
mio
9ec6b0be94 Add a test for fpr 2025-02-17 20:23:50 +08:00
mio
c97449869d Format code 2025-02-17 20:17:10 +08:00
@Antelox
8d52ece48b Replaced custom deprecated decorator with simple DeprecationWarning (#2110) 2025-02-16 23:04:42 +08:00
mio
7ec987e626 Basic test for previous regression 2025-02-15 20:17:18 +08:00
Amaan Qureshi
6b9c1c851c fix(arm): correct write to ARM coprocessor (#2099)
This code was commented out since 2021, but by default, the error
codewas initialized to `UC_REG_OK`, so there was no error returned
untila result, any write to `UC_ARM_REG_C1_C0_2` returned an error.
2025-02-13 19:25:26 +08:00
@Antelox
dea3c376d0 CI(full),CI(release): Python bindings: (#2100)
- Switched to the ubuntu-24.04-arm runner
- Bumped Windows runner to windows-2022 and Visual Studio 17 2022 GENERATORS
- Minor changes about checks in workflow jobs
- Fixed the pagefile job (even though should not be really needed)
- Refreshed the TO BE CHECKED regress tests to either update or remove the skip conditions
- Added a test to check if the created sdist archive is ok
2025-02-13 18:24:04 +08:00
mio
c915d13cce Fix pc issue of tcg opcode hooks 2025-02-10 21:35:17 +08:00
mio
a903fa182b Avoid null ptr deref when writing to arm context pc register 2025-02-10 15:58:28 +08:00
dotcirill
dc1f7a88d5 Uc hook tcg improve (#2011)
* Add handling UC_TCG_OP_FLAG_CMP for ARM

Implementation is not well-tested and complete

* Hook ARM32 CMP and CMN for cmplog
2025-02-10 15:01:21 +08:00
xndcn
1ba25def8e Fix UC_HOOK_MEM on arm32 (#2091) 2025-01-26 13:28:24 +08:00
ZakDanger
d7c0497ee3 Added start in mips16 mode support, and unit test for it - on dev branch (#2089)
Co-authored-by: ZakDanger <ZakDanger@users.noreply.github.com>
2025-01-19 17:35:40 +08:00
7f6dcc7539 Test the pc is correctly sync-ed for arm64 2025-01-18 15:38:47 +08:00
ab565729e7 Format code 2025-01-18 15:18:49 +08:00
a0fa2c1249 Fix a warning 2025-01-18 15:18:37 +08:00
99c57a8ecf Add a test for #1643 2025-01-18 15:17:47 +08:00
Daniel Roethlisberger
9682fc42f7 Allow uc_ctl_set_page_size() for arm64 (#2084) 2025-01-07 11:03:34 +08:00
8720632764 Add the unit test from saicao
Co-authored-by: Sai Cao <1665673333@qq.com>
2025-01-04 19:00:22 +08:00
mio
80f0dac6f0 Fix warning 2025-01-04 17:21:02 +08:00
mio
2c688bae73 Remove the outdated hack to zero all code gen buffer
This shall also improve performance

Fix #2001
2025-01-04 17:05:34 +08:00
mio
fcca82bb28 Format code 2025-01-04 15:48:54 +08:00
mio
d50bbb5d5b Add unit test from #2078 2025-01-04 15:48:32 +08:00
mio
9e35265a97 Update docs for testing 2025-01-04 15:41:05 +08:00
Michael-c0de
4f417c3f11 patch multiple UC_HOOK_MEM callbacks for unaligned access (#2063)
* patch multiple UC_HOOK_MEM callbacks for unaligned access

* update test_x86.c for #2063

* update test_x86.c for build on win

---------

Co-authored-by: yaojiale2024@iscas.ac.cn <yaojiale2024@iscas.ac.cn>
Co-authored-by: lazymio <mio@lazym.io>
2024-12-29 23:24:32 +08:00
@Antelox
9cfd5cfac3 - Improved the GitHub python binding workflow: (#2072)
- Added fullMode input in workflow_dispatch
    - Take decision whether to build either in debug or release mode and if to build for all python versions according to the commit message patterns
    - Set proper artifact names
    - Removed not needed steps
    - Compacted some steps in order to leverage more the matrix feature
    - Bumped cibuildwheel action to 2.22.0
    - Run actual regress tests in place of sample scripts
- Specify optional test install in pyproject.toml with proper requirements
- Derive package version from git tags
- Add GENERATORS env var support in setup.py to specify cmake generator and minor refactoring
- Minor cleanup/refactoring for the regress test suite
- Marked some regress tests with skipIf to skip them in case of old python versions
- Marked some failing regress tests to be checked with skipIf
2024-12-29 22:24:48 +08:00
Pedro Tôrres
7737e7b436 make i386 instructions RDTSC and RDTSCP hookable (#2066)
* instruction hooks for RDTSC and RDTSCP

Signed-off-by: Pedro Tôrres <t0rr3sp3dr0@gmail.com>

* update hookable instruction list

Signed-off-by: Pedro Tôrres <t0rr3sp3dr0@gmail.com>

* test RDTSC and RDTSCP instruction hooks

Signed-off-by: Pedro Tôrres <t0rr3sp3dr0@gmail.com>

---------

Signed-off-by: Pedro Tôrres <t0rr3sp3dr0@gmail.com>
Co-authored-by: mio <mio@lazym.io>
2024-12-20 17:17:23 +08:00
69200d4f00 Fix regression: If invalid instruction is handled, allow emulation to continue 2024-12-07 17:30:45 +08:00
9750d6e2fc QoL changes 2024-12-07 15:57:51 +08:00
Sai Ashwin
3a01515367 Rust Bindings: reg_read_batch and reg_write_batch (#2060)
* Added binding for rust reg_{read,write}_batch

* Fix reg_write_batch values pointer
2024-12-07 14:49:23 +08:00
Martin Atkins
7d8fe2ab11 riscv: Expose privilege level as pseudo-register PRIV (#1989)
Unlike some other architectures, RISC-V does not expose the current
privilege mode in any architecturally-defined register. That is intentional
to make it easier to implement virtualization in software, but a Unicorn
caller operates outside of the emulated hart and so it can and should be
able to observe and change the current privilege mode in order to properly
emulate certain behaviors of a real CPU.

The current privilege level is therefore now exposed as a new
pseudo-register using the name "priv", which matches the name of the
virtual register used by RISC-V's debug extension to allow the debugger
to read and change the privilege mode while the hart is halted. Unicorn's
use of it is conceptually similar to a debugger.

The bit encoding of this register is the same as specified in RISC-V Debug
Specification v1.0-rc3 Section 4.10.1. It's defined as a "virtual"
register exposing a subset of fields from the dcsr register, although here
it's implemented directly inside the Unicorn code because QEMU doesn't
currently have explicit support for the CSRs from the debug specification.
If it supports "dcsr" in a future release then this implementation could
change to wrap reading and writing that CSR and then projecting the "prv"
and "v" bitfields into the correct locations for the virtual register.
2024-11-11 21:09:45 +08:00
PhilippTakacs
ab23d4ceb0 Optimize Notdirty write (#2031)
* enable notdirty_write for snapshots when possible

Snapshots only happens when the priority of the memory region is smaller
then the snapshot_level. After a snapshot notdirty can be set.

* disable notdirty_write for self modifying code

When SMC access the memory region more then once the
tb must be rebuild multible times.

fixes #2029

* notdirty_write better hook check

Check all relevant memory hooks before enabling notdirty write.
This also checks if the memory hook is registered for the affected
region. So it is possible to use notdirty write and have some hooks
on different addresses.

* notdirty_write check for addr_write in snapshot case

* self modifying code clear recursive mem access

when self modifying code does unaligned memory accese sometimes
uc->size_recur_mem is changed but for notdirty write not changed back.
This causes mem_hooks to be missed. To fix this uc->size_recur_mem is
set to 0 before each cpu_exec() call.
2024-11-01 00:02:11 +08:00
PhilippTakacs
e8ca3cbea5 Optimize memory handling (#1963)
* optimize ram block handling

Save the last element of the ram_list. This allows to
faster find where to add new elements when they are not
bigger then page size.

* save ram_list freed

this keeps the optimization for find_ram_offset() intact after snapshot
restore.

* cow only clear the tlb of affected pages

* update flatview when possible

Building each flatview new when the memory has changed is quite
expensive when many MemoryRegions are used. This is an issue when using
snapshots.

* update benchmark for new api

* save flatview in context

this avoids rebuilding the flatview when restore a context.

* init context flatview with zero

* address_space_dispatch_clear remove subpage with higher priority

* docutemnt the options for UC_CTL_CONTEXT_MODE

Specialy stress that with UC_CTL_CONTEXT_MEMORY it is not possible to
use the context with a different unicorn object.
2024-10-16 21:51:13 +08:00
Eli
fea3411803 Minor Python regress fixes (#2030)
* Fix erronous method name

* Uncomment known failures

* Opportunistic improvements
2024-10-13 16:35:42 +08:00
mio
fbf34af81c Fix off-by-one bug and add a unit test 2024-10-13 15:19:05 +08:00
Eli
9f578946d5 Revamp Python regression tests suite (#2022)
* Fix Python regression test suite (partial)

* Fix Python regression test suite

* Add a test for mapping at high addresses

* Add ctl tests
2024-10-13 13:14:10 +08:00
0886e53572 Format code 2024-10-06 23:32:16 +08:00
851914c8d0 Fix segfault if tlb is flushed in the hooks 2024-10-06 23:31:46 +08:00
Eli
ac4872be4c Support additional API on Python 3 bindings (#2016)
* Styling and commets fixes

* Add errno API support

* Improve OOP approach by adjusting the way reg types are selected

* Leverage new approach to deduplicate reg_read and reg_write code

* Adjust reg_read_batch

* Add support for reg_write_batch

* Adjust x86 MSR accessors

* Turn asserts into descriptive exceptions

* Improve comments and styling

* Fix ARM memcpy neon regression test

* Modify canonicals import

* Introduce ARM CP reg accessors
2024-10-06 23:14:03 +08:00
mio
87c0b86248 Format code 2024-09-21 17:59:23 +08:00
Duncan Ogilvie
87610baa3f Fix emulator detection (#1966)
* Add a quick test helper macro to test_x86.c

* Add regression tests for bswap and rex prefixes

* Properly ignore REX prefixes when appropriate

* Fix bswap ax emulator detection
2024-07-19 11:11:21 +08:00
PhilippTakacs
7d8b06b704 snapshot restore don't remove terminating regions (#1968) 2024-06-29 22:36:02 +08:00
Nguyen Anh Quynh
c136b6b2bf fix some compiler warnings 2024-04-22 20:03:07 +08:00
227ff1d8bd Merge pull request #1928 from mlgiraud/feat/add_start_end_to_hook
Feature: Bindings: add start end to block hook
2024-03-11 19:50:46 +08:00
Mark Giraud
d4f5bf1be2 fix: Fix rust test that was missing a parameter 2024-03-11 12:31:54 +01:00
d1da4de080 Merge pull request #1929 from xclusivor/master
Remove semicolons in python files
2024-03-08 15:10:58 +08:00
xclusivor
4a694d8a30 remove semicolons 2024-03-06 02:15:02 -05:00