Commit Graph

169 Commits

Author SHA1 Message Date
mio
ffeddd7579 use qemu_memalign for all cpu structs
Some structs, specically CPUARMState is 16-bytes aligned.

This causes segment fault because gcc tends to vectorize

the assignment of the struct with infamous movaps tricks.

Without this patch, we fail on manylinux with 2.17 glibc

in release mode in i686.

qemu_memalign will ensure the alignment across platforms.
2024-10-17 13:50:07 +08:00
0886e53572 Format code 2024-10-06 23:32:16 +08:00
mio
05e29b4507 Implement UC_ARM64_REG_WSP 2024-10-02 16:03:59 +08:00
mio
9f935f505e Revert previous break changes that return UC_ERR_ARG for non-existing registers
But print a warning instead
2024-10-02 16:03:58 +08:00
elicn
ff06b145e1 Fix I0-7 registers write 2024-09-30 18:52:37 +03:00
elicn
9af1df6543 Add read and write support for i386 ZMM0-31 2024-09-28 22:17:06 +03:00
elicn
5164dbd609 Add read and write support for i386 YMM8-31 2024-09-28 22:16:45 +03:00
elicn
e3675162ba Add read and write support for i386 XMM16-31 2024-09-28 22:15:00 +03:00
elicn
6cb9bfe5c0 Avoid updating CR3 when writing CR1 and CR2 2024-09-28 22:11:54 +03:00
elicn
433bb163d9 Add read and write cases for i386 CR8 2024-09-28 22:11:01 +03:00
9427f0a553 Merge pull request #1991 from apparentlymart/b-riscv-invalidinsn-pcadj
riscv: Invalid 32-bit instruction should not decrement pc
2024-09-21 18:26:59 +08:00
Jose Martins
58f1a612e8 target/riscv: fix wfi exception behavior
The wfi exception trigger behavior should take into account user mode,
hstatus.vtw, and the fact the an wfi might raise different types of
exceptions depending on various factors:

If supervisor mode is not present:

- an illegal instruction exception should be generated if user mode
executes and wfi instruction and mstatus.tw = 1.

If supervisor mode is present:

- when a wfi instruction is executed, an illegal exception should be triggered
if either the current mode is user or the mode is supervisor and mstatus.tw is
set.

Plus, if the hypervisor extensions are enabled:

- a virtual instruction exception should be raised when a wfi is executed from
virtual-user or virtual-supervisor and hstatus.vtw is set.

Signed-off-by: Jose Martins <josemartins90@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210420213656.85148-1-josemartins90@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-09-03 13:44:55 -07:00
Martin Atkins
ac1b37421d riscv: Invalid 32-bit instruction should not decrement pc
This line appears to be trying to undo the effect of adding 4 to pc above,
but does so incorrectly and so ends up returning with next_pc earlier than
it was prior to decoding.

This causes the translator to malfunction because it does not expect
pc_next to decrease during decoding: this is effectively reporting that
the invalid construction has a negative size, which is impossible. The
decoder uses the increase in next_pc to decide the translation block size,
but converts it to uint16_t thereby causing a block containing _only_ an
invalid instruction to be treated as having size 65532 (reinterpreted -4)
and therefore the translation loop tries to find the next translation block
at 65532 bytes after the invalid instruction, which can cause a spurious
instruction access/page fault if the page containing that address is not
mapped as executable.

In practice we don't need to readjust the pc at all here because it is
correct to report that the invalid instruction is four bytes long. This
allows the translation loop to correctly find the next instruction, and
to avoid producing spurious TLB fills that might cause incorrect exceptions.
2024-08-28 14:06:17 -07:00
Duncan Ogilvie
87610baa3f Fix emulator detection (#1966)
* Add a quick test helper macro to test_x86.c

* Add regression tests for bswap and rex prefixes

* Properly ignore REX prefixes when appropriate

* Fix bswap ax emulator detection
2024-07-19 11:11:21 +08:00
BitMaskMixer
8e6499fb0b gcc compiler warning fixes (#1977)
* fix for enum-int-mismatch

* fix for unused-variable
2024-07-19 11:09:57 +08:00
Nguyen Anh Quynh
c136b6b2bf fix some compiler warnings 2024-04-22 20:03:07 +08:00
mio
24f898fb58 Fix #1869 2024-02-15 15:22:32 +08:00
a6fb2a6870 Save jit state before/after callback 2024-02-13 11:13:01 +08:00
mio
3c64e9a9e7 Revert previous wrong fixes 2024-01-03 18:06:09 +08:00
mio
02e3cba4c4 HAVE_ATOMIC128 is defined as a number 2024-01-03 17:45:04 +08:00
mio
3cff3eb2d5 Don't rely on dead code elimination 2024-01-03 16:50:28 +08:00
dotcirill
b0ea433772 Fix PPC32 fault when timer-spr access
Access to TB, DEC registers was lead to crash
spr_read_decr and others are changed to spr_read_generic
spr_write_decr and others are changed to spr_write_generic
2023-12-06 01:58:50 +03:00
StalkR
db63f2d9d7 qemu: fix UBSAN errors in tcg and arm translation 2023-11-14 10:23:50 +01:00
Dimitris Glynos
9d8e639c69 fix fxsave fpip value, provide tests 2023-10-26 08:42:58 +03:00
c889258d8e Avoid overwriting tmp0 2023-08-06 21:25:37 +08:00
basavesh
cf5e75953d Backport qemu/qemu@75b208c
target/i386: fix operand order for PDEP and PEXT

For PDEP and PEXT, the mask is provided in the memory (mod+r/m)
operand, and therefore is loaded in s->T0 by gen_ldst_modrm.
The source is provided in the second source operand (VEX.vvvv)
and therefore is loaded in s->T1. Fix the order in which
they are passed to the helpers.
2023-08-03 13:12:39 +02:00
mio
a7a5d187e7 Backport 10b8eb94c0
target/i386: Verify memory operand for lcall and ljmp

These two opcodes only allow a memory operand.

Lacking the check for a register operand, we used the A0 temp

without initialization, which led to a tcg abort.
2023-06-30 20:21:56 +08:00
mio
75676eb0cd Also rebuild flags for aarch32 2023-06-28 10:39:25 +08:00
Robert Xiao
30d202b89e Simplify reg_read/reg_write, obtaining a perf boost.
Single reg_read/reg_write is now about 25% faster.
2023-06-16 15:23:42 -07:00
Robert Xiao
074566cf69 Slight refactoring to reduce code duplication.
This also comes with a performance bump due to inlining of reg_read/reg_write
(as they're only called once now) and the unlikely() on CHECK_REG_TYPE.
2023-06-16 15:23:42 -07:00
Robert Xiao
4055a5ab10 Implement uc_reg_{read,write}{,_batch}2 APIs.
These APIs take size parameters, which can be used to properly bounds-check the
inputs and outputs for various registers. Additionally, all backends now throw
UC_ERR_ARG if the input register numbers are invalid.

Completes #1831.
2023-06-16 15:23:42 -07:00
Robert Xiao
d7a806c026 Reformat code with format.sh 2023-06-16 15:23:41 -07:00
mio
a24e53d794 Rebuild flags after writing to cp registers
This is buggy as this momemt per https://github.com/unicorn-engine/unicorn/issues/1789#issuecomment-1546807410

We need either doc this or save more information for a context
2023-05-14 13:35:31 +02:00
Takacs, Philipp
e96ac42b2e Remove MMU hacks
Unicorn has included some ugly hacks to provide a envirement where vaddr == paddr.
These hacks where to use the full 64 bit mappings on x86 without init the mmu
and some memory redirect for MIPS.

The UC_TLB_CPU mode defaults to vaddr == paddr, therfor these hacks aren't
required anymore.
2023-03-28 14:02:17 +02:00
Takacs, Philipp
e25419bb2d add virtuall tlb
this virtuall tlb allows to use mmu indipendent of the architectur
2023-03-28 13:50:11 +02:00
Takacs, Philipp
901034577a i386 call internal helper on special porpese register write
Some registers writes have side effects. i.e. write to cr3 flush the tlb,
if the PG bit is set.
2023-03-28 13:50:11 +02:00
Takacs, Philipp
f2eb1f4711 i386 mmu hack: Allow emulate usermode without mmu
This basicaly mappes virtual addresses to physical addresses 1:1 when
the mmu is disabled in the cpu. So you can use the full 64 bit addressspace
without required to configure the mmu.
2023-03-28 13:50:11 +02:00
Takacs, Philipp
b7b1a4d6b4 difference between stop_request and quit_request
quit_request is for internal use. This means the IP register was updated and
qemu needs to rebuild the translation blocks.

stop_request is set by the user (uc_emu_stop) to indecate that unicorn sould
stop emulating.
2023-03-07 14:38:49 +01:00
Takacs, Philipp
14404ef04b [x86] don't hardcode cpuid results
The cpuid results are set by the selected cpu.

CLOSES #1787
2023-02-27 12:34:38 +01:00
mio
133504b504 Fix wrong IP in x86_16 because of cs_base not substracted 2023-02-20 20:21:56 +01:00
Nguyen Anh Quynh
9dc001d686 remove unused code in PPC & dis-asm.h 2022-12-07 01:36:44 +08:00
mio
9c5358c759 Respect QEMU ZMM_Q to work on big endian hosts 2022-10-28 17:37:02 +02:00
mio
6162708bb2 Hack more to support BE32 2022-10-21 11:30:22 +02:00
mio
13b8e2625f Check PC range for mem hooks 2022-10-20 21:25:21 +02:00
mio
a5d4d30a31 Sync PC for mem ldst on aarch64 2022-10-20 21:19:18 +02:00
mio
35010035d7 Fix macro typo
Thanks @roehling
2022-10-20 20:10:27 +02:00
TSR Berry
442dd437e1 aarch64: Move FPCR and FPSR registers to not break compatibility
Co-authored-by: merry <git@mary.rs>
2022-10-14 17:31:20 +02:00
TSR Berry
12fd4fc086 aarch64: Add FPCR and FPSR registers
Co-authored-by: merry <git@mary.rs>
2022-10-14 15:18:14 +02:00
mio
19d8876e23 Deep copy for arm cpu state 2022-10-01 00:14:08 +02:00
5e060513a0 Merge pull request #1687 from relapids/clang_cl_support
Allow building with clang-cl (using MSVC config) on Windows.
2022-09-27 23:02:21 +02:00