Merge pull request #1991 from apparentlymart/b-riscv-invalidinsn-pcadj

riscv: Invalid 32-bit instruction should not decrement pc
2024-09-21 18:26:59 +08:00
parent 96bf47dd7a ac1b37421d
commit 9427f0a553
1 changed files with 0 additions and 1 deletions
--- a/qemu/target/riscv/translate.c
+++ b/qemu/target/riscv/translate.c
@@ -769,7 +769,6 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
                             translator_lduw(tcg_ctx, env, ctx->base.pc_next + 2));
        ctx->pc_succ_insn = ctx->base.pc_next + 4;
        if (!decode_insn32(ctx, opcode32)) {
-            ctx->pc_succ_insn = ctx->base.pc_next - 4;
            gen_exception_illegal(ctx);
        }
    }