Commit Graph

3233 Commits

Author SHA1 Message Date
9750d6e2fc QoL changes 2024-12-07 15:57:51 +08:00
9ec1f604dc Fix regression: Setting eflags within the hook should take effect
This add an extra compute_eflags after the hooks
2024-12-07 15:56:56 +08:00
@Antelox
f78a3f2f59 Python bindings: Fix editable install + Execute Python2.7 workflow tests (#2044)
* Python binding:
- Added missing `license` field in pyproject.toml file
- Fixed editable mode install and some more code cleanup in setup.py
- Refreshed README.md
- Replaced f-string formatter in tests with `format` method in order to be py2-compatible
- Fixed typos
- PEP8 fixes

* GitHub Action: Install Python2.7 and run tests for re-tagged wheels on native arch runners only

* Python bindings:
- Use #x formatter to format hex values
2024-12-07 14:52:21 +08:00
Sai Ashwin
3a01515367 Rust Bindings: reg_read_batch and reg_write_batch (#2060)
* Added binding for rust reg_{read,write}_batch

* Fix reg_write_batch values pointer
2024-12-07 14:49:23 +08:00
Martin Atkins
7d8fe2ab11 riscv: Expose privilege level as pseudo-register PRIV (#1989)
Unlike some other architectures, RISC-V does not expose the current
privilege mode in any architecturally-defined register. That is intentional
to make it easier to implement virtualization in software, but a Unicorn
caller operates outside of the emulated hart and so it can and should be
able to observe and change the current privilege mode in order to properly
emulate certain behaviors of a real CPU.

The current privilege level is therefore now exposed as a new
pseudo-register using the name "priv", which matches the name of the
virtual register used by RISC-V's debug extension to allow the debugger
to read and change the privilege mode while the hart is halted. Unicorn's
use of it is conceptually similar to a debugger.

The bit encoding of this register is the same as specified in RISC-V Debug
Specification v1.0-rc3 Section 4.10.1. It's defined as a "virtual"
register exposing a subset of fields from the dcsr register, although here
it's implemented directly inside the Unicorn code because QEMU doesn't
currently have explicit support for the CSRs from the debug specification.
If it supports "dcsr" in a future release then this implementation could
change to wrap reading and writing that CSR and then projecting the "prv"
and "v" bitfields into the correct locations for the virtual register.
2024-11-11 21:09:45 +08:00
tbodt
f71bc1a115 Several bugfixes (#2049)
* Remove global variable from aarch64 tcg target

This obviously breaks trying to run two unicorn instances at once on
aarch64. It appears a similar variable had already been moved to the
state struct for i386 tcg target.

* Reenable writing to jit region while calling tb_add_jump

On arm macs, every place that writes to jit code needs to have
tb_exec_unlock called first. This is already in most necessary places,
but not this one.

* Don't forget to call restore_jit_state in uc_context_restore

Every time UC_INIT is used, restore_jit_state must be used on the return
path, or occasional assertion failures will pop up on arm macs.

* Restore pc before calling into tlb fill hook

In my application it is important to have correct pc values available
from this hook.
2024-11-04 12:53:26 +08:00
PhilippTakacs
ab23d4ceb0 Optimize Notdirty write (#2031)
* enable notdirty_write for snapshots when possible

Snapshots only happens when the priority of the memory region is smaller
then the snapshot_level. After a snapshot notdirty can be set.

* disable notdirty_write for self modifying code

When SMC access the memory region more then once the
tb must be rebuild multible times.

fixes #2029

* notdirty_write better hook check

Check all relevant memory hooks before enabling notdirty write.
This also checks if the memory hook is registered for the affected
region. So it is possible to use notdirty write and have some hooks
on different addresses.

* notdirty_write check for addr_write in snapshot case

* self modifying code clear recursive mem access

when self modifying code does unaligned memory accese sometimes
uc->size_recur_mem is changed but for notdirty write not changed back.
This causes mem_hooks to be missed. To fix this uc->size_recur_mem is
set to 0 before each cpu_exec() call.
2024-11-01 00:02:11 +08:00
Eli
957df0ec3a Fix TLB fill hook (#2042)
* Fix the TLB fill hook

* Add missing annotations
2024-10-25 20:22:53 +08:00
16916b2f1e Fix small typo 2024-10-19 16:32:43 +08:00
Eli
28ff8d8627 Hook tlb fill (#2037)
* Support TLB fill hooks

* Improve consistency among structure names
2024-10-18 23:22:04 +08:00
@Antelox
3691e33a0f Feat: Option to manually specify the build type in the workflow (#2034)
* Python bindings: Fix upload-artifact actions

* Github Action: Enable workflow_dispatch to manually trigger jobs to produce either Debug or Release builds
2024-10-17 21:15:56 +08:00
@Antelox
6fbbf3089a Python binding setup refactoring + cibuildwheel workflow (#2026)
* Python bindings: Make the test scripts handy for pytest

* Python bindings: Update MANIFEST.in with new paths

* Update .gitignore to exclude PyCharm-related files/folders

* Python bindings: Update CMakeLists.txt in order to set CMAKE_OSX_ARCHITECTURES var

* Python bindings:
- Moved project package settings to the new TOML format
- Refactored setup.py to cleanup/improve the code and make it ready for cibuildwheel
- Updated README.md with the package long description part
- Removed setup.cfg since universal wheel building will be deprecated soon

* Python bindings:
- Replaced old PyPI-publishing.yml workflow with brand-new one based on cibuildwheel
- Removed old building scripts

* Replaced macos-12 runner with macos-13 since it will be removed soon

* Python bindings: Specify SYSTEM_VERSION_COMPAT=0 env var for macos-13 x86_64 runner as per cibuildwheel warning message

* Python bindings: Enable i686 for debugging

* Python bindings: Enable DEBUG flag according to the presence of tag release

* Python bindings: Added matrix to cover i686 manylinux/musllinux builds

* Python bindings:
- Replaced macos-14 runner with macos-latest
- Bumped cibuildwheel GitHub action to 2.21.3 version

* Python bindings:
- Adapt test_uc_ctl_tb_cache test to the recent changes
- Fixed typos
- PEP8 fixes

* GitHub Action Workflow: Introduce BUILD_TYPE env var to select build type according to the presence of tag release

---------

Co-authored-by: mio <mio@lazym.io>
2024-10-17 19:35:42 +08:00
mio
c42cc0fe86 More 16-bits aligned cpu state targets 2024-10-17 16:33:59 +08:00
mio
ffeddd7579 use qemu_memalign for all cpu structs
Some structs, specically CPUARMState is 16-bytes aligned.

This causes segment fault because gcc tends to vectorize

the assignment of the struct with infamous movaps tricks.

Without this patch, we fail on manylinux with 2.17 glibc

in release mode in i686.

qemu_memalign will ensure the alignment across platforms.
2024-10-17 13:50:07 +08:00
PhilippTakacs
e8ca3cbea5 Optimize memory handling (#1963)
* optimize ram block handling

Save the last element of the ram_list. This allows to
faster find where to add new elements when they are not
bigger then page size.

* save ram_list freed

this keeps the optimization for find_ram_offset() intact after snapshot
restore.

* cow only clear the tlb of affected pages

* update flatview when possible

Building each flatview new when the memory has changed is quite
expensive when many MemoryRegions are used. This is an issue when using
snapshots.

* update benchmark for new api

* save flatview in context

this avoids rebuilding the flatview when restore a context.

* init context flatview with zero

* address_space_dispatch_clear remove subpage with higher priority

* docutemnt the options for UC_CTL_CONTEXT_MODE

Specialy stress that with UC_CTL_CONTEXT_MEMORY it is not possible to
use the context with a different unicorn object.
2024-10-16 21:51:13 +08:00
Eli
fea3411803 Minor Python regress fixes (#2030)
* Fix erronous method name

* Uncomment known failures

* Opportunistic improvements
2024-10-13 16:35:42 +08:00
mio
7e32864774 Also include cmake directory in sdist 2024-10-13 16:34:25 +08:00
mio
fbf34af81c Fix off-by-one bug and add a unit test 2024-10-13 15:19:05 +08:00
mio
579317bb21 Fix memory leak of g_array_free 2024-10-13 13:39:57 +08:00
Eli
9f578946d5 Revamp Python regression tests suite (#2022)
* Fix Python regression test suite (partial)

* Fix Python regression test suite

* Add a test for mapping at high addresses

* Add ctl tests
2024-10-13 13:14:10 +08:00
Eli
78580ca8f9 Python3 bindings improvements (#2024)
* Allow Uc subclasses to use additional constructor args

* Add missing conext reg write batch prorotype

* Sort uc prototypes for better readability

* Redefine internal C API structures

* Add ctypes alises to improve readability

* Added documentation for ctl methods

* Added ctl tcg buffer size accessors

* Fix tcg buffer size return type
2024-10-09 14:13:42 +08:00
Daniel Roethlisberger
26268e69af python: Fix assertion failure on ctl_flush_tb() (#2023) 2024-10-08 12:48:05 +08:00
0886e53572 Format code 2024-10-06 23:32:16 +08:00
851914c8d0 Fix segfault if tlb is flushed in the hooks 2024-10-06 23:31:46 +08:00
Eli
ac4872be4c Support additional API on Python 3 bindings (#2016)
* Styling and commets fixes

* Add errno API support

* Improve OOP approach by adjusting the way reg types are selected

* Leverage new approach to deduplicate reg_read and reg_write code

* Adjust reg_read_batch

* Add support for reg_write_batch

* Adjust x86 MSR accessors

* Turn asserts into descriptive exceptions

* Improve comments and styling

* Fix ARM memcpy neon regression test

* Modify canonicals import

* Introduce ARM CP reg accessors
2024-10-06 23:14:03 +08:00
mio
05e29b4507 Implement UC_ARM64_REG_WSP 2024-10-02 16:03:59 +08:00
mio
d30ba77c71 Refine warning 2024-10-02 16:03:58 +08:00
mio
9f935f505e Revert previous break changes that return UC_ERR_ARG for non-existing registers
But print a warning instead
2024-10-02 16:03:58 +08:00
mio
a637368122 Add .gdb_history 2024-10-02 16:03:58 +08:00
mio
07e67c6570 Remove gdb history 2024-10-02 16:03:57 +08:00
d9b66c4b74 Merge pull request #2017 from elicn/fix-sparc
Fix SPARC I0-7 registers write
2024-10-01 00:03:09 +08:00
elicn
ff06b145e1 Fix I0-7 registers write 2024-09-30 18:52:37 +03:00
35a6b14f1e Merge pull request #2014 from elicn/more-x86-regs
Add support for more Intel registers
2024-09-29 14:13:13 +08:00
elicn
9af1df6543 Add read and write support for i386 ZMM0-31 2024-09-28 22:17:06 +03:00
elicn
5164dbd609 Add read and write support for i386 YMM8-31 2024-09-28 22:16:45 +03:00
elicn
e3675162ba Add read and write support for i386 XMM16-31 2024-09-28 22:15:00 +03:00
elicn
6cb9bfe5c0 Avoid updating CR3 when writing CR1 and CR2 2024-09-28 22:11:54 +03:00
elicn
433bb163d9 Add read and write cases for i386 CR8 2024-09-28 22:11:01 +03:00
mio
91122b6a68 Fix compatibility of 3.8 2024-09-26 23:02:03 +08:00
mio
d568885d64 Re-add muls_wheel.sh
Thanks to @Antelox

Co-authored-by: @Antelox <anteloxrce@gmail.com>
2024-09-26 19:15:03 +08:00
mio
050f2fbcaf temp remove 2024-09-26 19:13:57 +08:00
mio
9e0addd682 Still add plat-name for Linux 2024-09-26 19:11:53 +08:00
mio
2ccdc08237 Fix musl build script 2024-09-26 18:47:20 +08:00
mio
867770c7ef Tag and release 2.1.1 2024-09-26 18:44:51 +08:00
mio
4fa34d43ef Fix arm64 wheel
93542c397c/cibuildwheel/macos.py (L247-L260)

We shall really migrate to cibuildwheel
2024-09-26 18:38:23 +08:00
mio
9f89428abf Update changelog for 2.1.1 2024-09-26 18:15:48 +08:00
mio
869968a96f Only publish when tagging 2024-09-26 18:13:43 +08:00
mio
8bd254c6f5 Update changelog 2024-09-26 17:28:54 +08:00
mio
d645848fd3 Fix macos wheels 2024-09-26 17:26:16 +08:00
mio
08e14abf70 Remove hacks for bdist_wheel 2024-09-26 17:18:36 +08:00