Commit Graph

2618 Commits

Author SHA1 Message Date
mio
bdb141aeef Disable unaligned access test on ppc and aarch64
The memoy read operations on these architectures are inlined

e.g. ldur on aarch64
2022-08-14 15:42:37 +02:00
mio
419d710c4a Return true when we handled the memory events 2022-08-14 13:37:25 +02:00
mio
2c00546c6e Merge rhelmot's fix 2022-08-14 13:35:54 +02:00
mio
01e8d969c8 Update to r25
Ref: https://github.com/actions/runner-images/issues/5930
2022-08-14 12:56:52 +02:00
mio
8303328aa8 Obtain memory mapping after hooks are called 2022-08-14 12:42:53 +02:00
ffb047fe37 Merge pull request #1668 from Yu3H0/fix_tricore_pc_problem
fix issue 1663:tricore pc don't move
2022-07-26 22:08:43 +08:00
Yu3h0
ca6a8b4cac fix issue 1663:tricore pc don't move 2022-07-26 13:41:13 +08:00
mio
3d028882ed Fix wrong cput model check in uc_ctl 2022-07-23 20:49:00 +08:00
mio
6db6790ec2 Merge remote-tracking branch 'zachesez/ppc_cr_read_fix' into dev 2022-07-23 20:46:40 +08:00
mio
6d283cf464 Fix ppc symbols clash 2022-07-23 20:39:55 +08:00
mio
06a1858ffd Disable ming32 test 2022-07-23 20:39:55 +08:00
Mio
d6d57834b0 Format code 2022-07-23 19:27:37 +08:00
Mio
c7ff9d66cf Move vex.l test to test_x86 2022-07-23 19:26:35 +08:00
Mio
2efee81df3 Merge remote-tracking branch 'mrexoida/avx-bug' into dev 2022-07-23 19:26:07 +08:00
Mio
5b5905695d Fix wrong location of UC_ARM64_REG_CP_REG in python bindings 2022-07-23 19:21:31 +08:00
Zach Szczesniak
2b25867e4b Fixed endianness when writing PPC32 CR register. 2022-07-20 18:31:13 -04:00
Duncan Ogilvie
e485f39846 Add a test to make sure VEX.L stops emulation with an error 2022-07-20 13:59:27 +02:00
Duncan Ogilvie
22ea31cdf7 Fail when VEX.L is set in SSE instructions (AVX is not supported)
Closes #1656
2022-07-20 13:48:31 +02:00
Nguyen Anh Quynh
6c1cbef6ac Merge branch 'dev' 2022-07-07 23:49:09 +08:00
Nguyen Anh Quynh
1ec1352995 bindings: update consts 2022-07-07 23:48:01 +08:00
Nguyen Anh Quynh
492cdfe3d4 Changelog 2022-07-07 23:40:09 +08:00
Mio
e793dc65c2 Update changelog 2022-07-06 09:41:38 +08:00
Mio
af1c661a12 Update bindings 2022-07-06 09:33:45 +08:00
Mio
db8c04a07c Fix value collision between UC_MODE_ARMBE8 and UC_MODE_ARM926 2022-07-04 22:35:16 +08:00
Nguyen Anh Quynh
5552085115 add SECURITY.md 2022-07-03 22:34:51 +08:00
Nguyen Anh Quynh
c63bbff7d1 add SECURITY.md 2022-07-03 22:34:37 +08:00
0ebac3b455 Fix typo 2022-06-02 15:06:50 +02:00
6d61aec82f Format code 2022-06-02 14:46:26 +02:00
fdd129fd30 Remember the regions a hook has intrumented and clear cache on deletion 2022-06-02 14:46:02 +02:00
637dc8a8a0 Generate an extra block to trigger segfault 2022-06-02 14:45:38 +02:00
40436e885b Fix the cached hook test 2022-06-02 14:38:53 +02:00
774c942143 Add a test for hook cache UAF
If a hook is deleted but wrongly cached, a UAP is probably triggered
2022-06-01 23:58:02 +02:00
739fa45f50 Remove unused mmio 2022-06-01 23:43:53 +02:00
e3613a9f59 Format code 2022-05-28 23:46:18 +02:00
289034538d Cleaner implementation for uc_mem_prot on mmio regions 2022-05-28 23:46:06 +02:00
2a6529348c Support uc_mem_protect on mmio regions
Also make mmio ranges return the correct errors on wrong protection
2022-05-28 23:33:43 +02:00
6a2e2a1291 Minor fix for CMakeLists.txt 2022-05-23 22:29:07 +02:00
ac73e6b9d3 Fix #1623
The reg_id is left out
2022-05-23 20:23:55 +02:00
83444c1549 Update changelog 2022-05-23 12:35:19 +02:00
e5126f17f1 Bump version in bindings 2022-05-23 12:34:09 +02:00
ba50035830 Format code 2022-05-23 12:30:44 +02:00
17fa839a56 Eliminate more warnings in s390x 2022-05-21 00:07:20 +02:00
82d1c9e925 Eliminate warnings 2022-05-21 00:02:29 +02:00
9167ab8671 Set riscv_get_pc for uc->get_pc 2022-05-21 00:02:22 +02:00
cc4ed6ee50 Merge pull request #1621 from ondryaso/dev-registers
Support reads and writes over all Arm SIMD registers
2022-05-20 14:48:59 +02:00
dae48aecee Mem hook should return a bool 2022-05-20 13:31:54 +02:00
5d37e21db5 Don't call hooks if there is already an unhandled exception 2022-05-20 13:15:23 +02:00
0d41d4bbb2 Merge QDucasse:x86_hook_address for tests 2022-05-20 13:07:49 +02:00
Ondřej Ondryáš
f3b776dd7d Support reads and writes over all Arm SIMD registers 2022-05-20 00:30:11 +02:00
c1a391cb6b Update FAQ 2022-05-18 15:01:20 +02:00