* Support mips64 - write correct pc register width on uc_emu_start
* Convert to UC_MODE_MIPS64
* Correctly select MIPS64 CPU model
* Simple 64-bit test - check it doesn't crash
* lint
* Comment
* Comment
* Add offset when indexing cpu model, makes tests work on older python
* Move test
* add PC check to test
* Fix test - add python version check
* Use RegressTest method for assert
- Switched to the ubuntu-24.04-arm runner
- Bumped Windows runner to windows-2022 and Visual Studio 17 2022 GENERATORS
- Minor changes about checks in workflow jobs
- Fixed the pagefile job (even though should not be really needed)
- Refreshed the TO BE CHECKED regress tests to either update or remove the skip conditions
- Added a test to check if the created sdist archive is ok
- Added fullMode input in workflow_dispatch
- Take decision whether to build either in debug or release mode and if to build for all python versions according to the commit message patterns
- Set proper artifact names
- Removed not needed steps
- Compacted some steps in order to leverage more the matrix feature
- Bumped cibuildwheel action to 2.22.0
- Run actual regress tests in place of sample scripts
- Specify optional test install in pyproject.toml with proper requirements
- Derive package version from git tags
- Add GENERATORS env var support in setup.py to specify cmake generator and minor refactoring
- Minor cleanup/refactoring for the regress test suite
- Marked some regress tests with skipIf to skip them in case of old python versions
- Marked some failing regress tests to be checked with skipIf
* Styling and commets fixes
* Add errno API support
* Improve OOP approach by adjusting the way reg types are selected
* Leverage new approach to deduplicate reg_read and reg_write code
* Adjust reg_read_batch
* Add support for reg_write_batch
* Adjust x86 MSR accessors
* Turn asserts into descriptive exceptions
* Improve comments and styling
* Fix ARM memcpy neon regression test
* Modify canonicals import
* Introduce ARM CP reg accessors
- Q flag / GE flag were not included in APSR register (read/write)
- UC_ARM_REG_APSR_NZCV register constant was ignored completely.
- regression test added
* Adding regression test for issue where writing memory into a read only segment during a access callback fails.
* Check for TLB invalidation when calling read callbacks; Writes to read-only memory by the callback cause a TLB flush which requires a re-read of the TLB.
* Fixed the decoding of opcodes after getting vex2 using 0xc5
* Added testcase for vex. Can and should be expanded
* Fixed warning of testcase for vex (parentheses for assignment)
* Fuzzing M68K without abort
* UC_MODE_32 is not ok with sparc
use UC_MODE_SPARC32|UC_MODE_BIG_ENDIAN instead
* Temporary removing leaking on start targets
* Do not abort for m68K undef instructions
Adds SYSENTER to the whitelist of supported hookable instructions in unicorn
as well as fixes up the existing sysenter_hook_x86 regression test which was
previously failing
Fixesunicorn-engine/unicorn#995
* add x86_64_msr.py test demonstrating setting MSRs and FS/GS segments
* x86_64_msr.py: remove references to hooks
* x86_64_msr.py: remove references to old global variable
* reg_read and reg_write now work with registers W0 through W30 in Aarch64 emulaton
* Added a regress test for the ARM64 reg_read and reg_write on 32-bit registers (W0-W30)
Added a new macro in uc_priv.h (WRITE_DWORD_TO_QWORD), in order to write to the lower 32 bits of a 64 bit value without overwriting the whole value when using reg_write
* Fixed WRITE_DWORD macro
reg_write would zero out the high order bits when writing to 32 bit registers
e.g. uc.reg_write(UC_X86_REG_EAX, 0) would also set register RAX to zero
