Commit Graph

274 Commits

Author SHA1 Message Date
mio
8dcaa33c66 Bump 2.1.3 2025-02-17 20:26:31 +08:00
mio
c97449869d Format code 2025-02-17 20:17:10 +08:00
mio
0c6f7c60d5 Implement mips floating point related registers 2025-02-17 20:16:36 +08:00
mio
b8e19b6eef CI(release): Bump 2.1.2 2025-02-10 22:11:12 +08:00
mio
48fb28dfbc Update documents for MMU access 2025-02-10 15:36:03 +08:00
ab565729e7 Format code 2025-01-18 15:18:49 +08:00
mio
fcca82bb28 Format code 2025-01-04 15:48:54 +08:00
Martin Atkins
7d8fe2ab11 riscv: Expose privilege level as pseudo-register PRIV (#1989)
Unlike some other architectures, RISC-V does not expose the current
privilege mode in any architecturally-defined register. That is intentional
to make it easier to implement virtualization in software, but a Unicorn
caller operates outside of the emulated hart and so it can and should be
able to observe and change the current privilege mode in order to properly
emulate certain behaviors of a real CPU.

The current privilege level is therefore now exposed as a new
pseudo-register using the name "priv", which matches the name of the
virtual register used by RISC-V's debug extension to allow the debugger
to read and change the privilege mode while the hart is halted. Unicorn's
use of it is conceptually similar to a debugger.

The bit encoding of this register is the same as specified in RISC-V Debug
Specification v1.0-rc3 Section 4.10.1. It's defined as a "virtual"
register exposing a subset of fields from the dcsr register, although here
it's implemented directly inside the Unicorn code because QEMU doesn't
currently have explicit support for the CSRs from the debug specification.
If it supports "dcsr" in a future release then this implementation could
change to wrap reading and writing that CSR and then projecting the "prv"
and "v" bitfields into the correct locations for the virtual register.
2024-11-11 21:09:45 +08:00
PhilippTakacs
e8ca3cbea5 Optimize memory handling (#1963)
* optimize ram block handling

Save the last element of the ram_list. This allows to
faster find where to add new elements when they are not
bigger then page size.

* save ram_list freed

this keeps the optimization for find_ram_offset() intact after snapshot
restore.

* cow only clear the tlb of affected pages

* update flatview when possible

Building each flatview new when the memory has changed is quite
expensive when many MemoryRegions are used. This is an issue when using
snapshots.

* update benchmark for new api

* save flatview in context

this avoids rebuilding the flatview when restore a context.

* init context flatview with zero

* address_space_dispatch_clear remove subpage with higher priority

* docutemnt the options for UC_CTL_CONTEXT_MODE

Specialy stress that with UC_CTL_CONTEXT_MEMORY it is not possible to
use the context with a different unicorn object.
2024-10-16 21:51:13 +08:00
0886e53572 Format code 2024-10-06 23:32:16 +08:00
mio
867770c7ef Tag and release 2.1.1 2024-09-26 18:44:51 +08:00
mio
67f08b1c27 Bump version and generate bindings 2024-09-21 23:00:57 +08:00
mio
87c0b86248 Format code 2024-09-21 17:59:23 +08:00
lockbox
321de00f36 [typo]: Correctly document address parameter in mem hook callbacks 2024-03-18 17:51:35 -04:00
43597af0ed Merge pull request #1833 from nneonneo/rework-java-api
Rework the Java bindings
2023-12-25 19:53:45 +08:00
6801e156aa Format code 2023-08-06 21:53:42 +08:00
Takacs, Philipp
716c8f1c4c handle snapshots over context_save context_restore 2023-07-11 11:51:44 +02:00
Takacs, Philipp
80bd825420 implement simple memory snapshot mechanismus
Uses Copy on Write to make it posible to restore the memory state after a snapshot
was made. To restore all MemoryRegions created after the snapshot are removed.
2023-07-11 11:51:40 +02:00
Robert Xiao
77d4a1d8b1 Fix definition of uc_version 2023-06-17 14:19:10 -07:00
Robert Xiao
2b80ab425b Return new UC_ERR_OVERFLOW instead of UC_ERR_NOMEM when reg buffer is too small 2023-06-16 15:30:59 -07:00
Robert Xiao
4055a5ab10 Implement uc_reg_{read,write}{,_batch}2 APIs.
These APIs take size parameters, which can be used to properly bounds-check the
inputs and outputs for various registers. Additionally, all backends now throw
UC_ERR_ARG if the input register numbers are invalid.

Completes #1831.
2023-06-16 15:23:42 -07:00
Robert Xiao
d7a806c026 Reformat code with format.sh 2023-06-16 15:23:41 -07:00
mio
49ccbde2d0 Leave out essential files
Co-authored-by: ζeh Matt <5415177+ZehMatt@users.noreply.github.com>
2023-06-10 23:44:05 +02:00
mio
8dffbc159c Add uc_ctl_get/set_tcg_buffer_size
We still need this API because the virtual memory address space of

32 bits os is only 4GB and we default need 1G per instance

Credits to @ZehMatt for original idea

Co-authored-by: ζeh Matt <5415177+ZehMatt@users.noreply.github.com>
2023-06-10 23:36:02 +02:00
mio
f8c7969d65 Revert "Add uc_ctl_get/set_tcg_buffer_size"
This reverts commit 3145e3c426 because not
properly co-authoer-ed.
2023-06-10 23:29:56 +02:00
mio
3145e3c426 Add uc_ctl_get/set_tcg_buffer_size 2023-06-10 16:08:29 +02:00
Takacs, Philipp
227e578660 move typedef definition of enum uc_mem_type
forword references to enum types are forbidden in C. Also C++ will
not build if this is used
2023-05-08 15:38:43 +02:00
Mio
45f22085f5 Update comments 2023-03-28 21:17:01 +08:00
Takacs, Philipp
8b2c477578 clear the TLB cache in uc_ctl_flush_tlb
uc_ctl_flush_tlb implies that the tlb is flushed. This change adds
UC_CTL_TLB_FLUSH which clears the TLB and set the uc_ctl_flush_tlb
alias to UC_CTL_TLB_FLUSH. Also adds a uc_ctl_flush_tb alias for
UC_CTL_TB_FLUSH.
2023-03-28 14:11:41 +02:00
Takacs, Philipp
e25419bb2d add virtuall tlb
this virtuall tlb allows to use mmu indipendent of the architectur
2023-03-28 13:50:11 +02:00
Nguyen Anh Quynh
6e9c6aea5f bump version to 2.0.2 2023-02-04 13:00:58 +08:00
mio
bdd9f4fa9a Bump version to 2.0.1 2022-11-01 10:06:22 +01:00
TSR Berry
442dd437e1 aarch64: Move FPCR and FPSR registers to not break compatibility
Co-authored-by: merry <git@mary.rs>
2022-10-14 17:31:20 +02:00
TSR Berry
12fd4fc086 aarch64: Add FPCR and FPSR registers
Co-authored-by: merry <git@mary.rs>
2022-10-14 15:18:14 +02:00
Mio
d6d57834b0 Format code 2022-07-23 19:27:37 +08:00
Mio
db8c04a07c Fix value collision between UC_MODE_ARMBE8 and UC_MODE_ARM926 2022-07-04 22:35:16 +08:00
e5126f17f1 Bump version in bindings 2022-05-23 12:34:09 +02:00
Eric Poole
cfee2139a0 TriCore Support (#1568)
* TriCore Support

python sample

* Update sample_tricore.py

Correct attribution

* Update sample_tricore.py

Fixed byte code to execute properly.

* Update sample_tricore.py

Removed testing artifact

* Added tricore msvc config-file.h

* Added STATIC to tricore config and added helper methods to symbol file generation.

* Update op_helper.c

Use built in crc32

* Fix tricore samples and small code blocks are now handled properly

* Add CPU types

* Generate bindings

* Format code

Co-authored-by: lazymio <mio@lazym.io>
2022-04-29 23:11:34 +02:00
4e22744679 Support flushing translation blocks and flush when we don't need count hook 2022-04-26 01:17:58 +02:00
8fd9ee3dd0 Bump unicorn version 2022-04-17 16:47:37 +02:00
c379d1bfe4 Format code 2022-04-16 17:50:12 +02:00
b136f08f2d Check CPU model for uc_ctl 2022-04-16 17:49:47 +02:00
Ilya Leoshkevich
28c4c665f0 Add "holes" to where the removed x86 registers used to be
A number of x86 registers were removed for #1440, causing a change in
numbering for many other registers. This is causing inconveniences at
the moment, e.g. it's not possible to use the Unicorn2 shared library
as a drop-in replacement for the Unicorn1 one.

Restore the old numbering.

Fixes #1492.
2022-03-22 11:31:58 +01:00
ce932e4c28 Update comments for uc_cb_insn_sys_t 2022-03-05 22:42:41 +01:00
e5207a1363 Implement UC_HOOK_INSN for aarch64 MRS/MSR/SYS/SYSL 2022-02-27 15:28:31 +01:00
Bet4
504b31b928 Update constants of bindings 2022-02-19 21:24:40 +08:00
27ef63cc8d Add UC_PPC_REG_CR 2022-02-15 22:07:53 +01:00
16e9efa4f5 Bump version 2022-02-13 09:56:10 +01:00
58fc952230 Remove armeb-softmmu and aarch64eb-softmmu 2022-02-12 14:15:54 +01:00
acbc134f46 Fixed width fields 2022-02-11 22:18:52 +01:00