Commit Graph

274 Commits

Author SHA1 Message Date
mio
d50bbb5d5b Add unit test from #2078 2025-01-04 15:48:32 +08:00
Michael-c0de
4f417c3f11 patch multiple UC_HOOK_MEM callbacks for unaligned access (#2063)
* patch multiple UC_HOOK_MEM callbacks for unaligned access

* update test_x86.c for #2063

* update test_x86.c for build on win

---------

Co-authored-by: yaojiale2024@iscas.ac.cn <yaojiale2024@iscas.ac.cn>
Co-authored-by: lazymio <mio@lazym.io>
2024-12-29 23:24:32 +08:00
Pedro Tôrres
7737e7b436 make i386 instructions RDTSC and RDTSCP hookable (#2066)
* instruction hooks for RDTSC and RDTSCP

Signed-off-by: Pedro Tôrres <t0rr3sp3dr0@gmail.com>

* update hookable instruction list

Signed-off-by: Pedro Tôrres <t0rr3sp3dr0@gmail.com>

* test RDTSC and RDTSCP instruction hooks

Signed-off-by: Pedro Tôrres <t0rr3sp3dr0@gmail.com>

---------

Signed-off-by: Pedro Tôrres <t0rr3sp3dr0@gmail.com>
Co-authored-by: mio <mio@lazym.io>
2024-12-20 17:17:23 +08:00
Martin Atkins
7d8fe2ab11 riscv: Expose privilege level as pseudo-register PRIV (#1989)
Unlike some other architectures, RISC-V does not expose the current
privilege mode in any architecturally-defined register. That is intentional
to make it easier to implement virtualization in software, but a Unicorn
caller operates outside of the emulated hart and so it can and should be
able to observe and change the current privilege mode in order to properly
emulate certain behaviors of a real CPU.

The current privilege level is therefore now exposed as a new
pseudo-register using the name "priv", which matches the name of the
virtual register used by RISC-V's debug extension to allow the debugger
to read and change the privilege mode while the hart is halted. Unicorn's
use of it is conceptually similar to a debugger.

The bit encoding of this register is the same as specified in RISC-V Debug
Specification v1.0-rc3 Section 4.10.1. It's defined as a "virtual"
register exposing a subset of fields from the dcsr register, although here
it's implemented directly inside the Unicorn code because QEMU doesn't
currently have explicit support for the CSRs from the debug specification.
If it supports "dcsr" in a future release then this implementation could
change to wrap reading and writing that CSR and then projecting the "prv"
and "v" bitfields into the correct locations for the virtual register.
2024-11-11 21:09:45 +08:00
PhilippTakacs
ab23d4ceb0 Optimize Notdirty write (#2031)
* enable notdirty_write for snapshots when possible

Snapshots only happens when the priority of the memory region is smaller
then the snapshot_level. After a snapshot notdirty can be set.

* disable notdirty_write for self modifying code

When SMC access the memory region more then once the
tb must be rebuild multible times.

fixes #2029

* notdirty_write better hook check

Check all relevant memory hooks before enabling notdirty write.
This also checks if the memory hook is registered for the affected
region. So it is possible to use notdirty write and have some hooks
on different addresses.

* notdirty_write check for addr_write in snapshot case

* self modifying code clear recursive mem access

when self modifying code does unaligned memory accese sometimes
uc->size_recur_mem is changed but for notdirty write not changed back.
This causes mem_hooks to be missed. To fix this uc->size_recur_mem is
set to 0 before each cpu_exec() call.
2024-11-01 00:02:11 +08:00
mio
fbf34af81c Fix off-by-one bug and add a unit test 2024-10-13 15:19:05 +08:00
0886e53572 Format code 2024-10-06 23:32:16 +08:00
851914c8d0 Fix segfault if tlb is flushed in the hooks 2024-10-06 23:31:46 +08:00
mio
87c0b86248 Format code 2024-09-21 17:59:23 +08:00
Duncan Ogilvie
87610baa3f Fix emulator detection (#1966)
* Add a quick test helper macro to test_x86.c

* Add regression tests for bswap and rex prefixes

* Properly ignore REX prefixes when appropriate

* Fix bswap ax emulator detection
2024-07-19 11:11:21 +08:00
PhilippTakacs
7d8b06b704 snapshot restore don't remove terminating regions (#1968) 2024-06-29 22:36:02 +08:00
Nguyen Anh Quynh
c136b6b2bf fix some compiler warnings 2024-04-22 20:03:07 +08:00
f3323469d0 Format 2024-02-12 00:10:58 +08:00
Takacs, Philipp
d9d2c4e581 fix uc_mem write with cow when using upper half of the address
uc->target_page_align is a uint32_t. When the binary not will only
invert the 32 bit of the value. Used this in a binary and operator with
a uint64_t will case the upper 32bit of the address to be 0. Therefor
the bug only appears when the upper 32bit of the address are used.

Now a local uint64_t variable is used for the alignemend and the test
uses a not page alligned address which does not fit in 32bit.
2024-01-15 14:20:29 +01:00
dotcirill
b0ea433772 Fix PPC32 fault when timer-spr access
Access to TB, DEC registers was lead to crash
spr_read_decr and others are changed to spr_read_generic
spr_write_decr and others are changed to spr_write_generic
2023-12-06 01:58:50 +03:00
Dimitris Glynos
9d8e639c69 fix fxsave fpip value, provide tests 2023-10-26 08:42:58 +03:00
Mark Giraud
f081af002a test: Add test to reproduce cow+vtlb error 2023-08-24 11:44:21 +02:00
6801e156aa Format code 2023-08-06 21:53:42 +08:00
30bc08611b Add a unit test for #1717 2023-08-06 21:53:04 +08:00
Takacs, Philipp
f6cfe1092b vtlb only cache access permisions required for the operation
see #1845
2023-07-17 12:54:38 +02:00
Takacs, Philipp
df18756234 implement uc_mem_unmap with snapshots
still has todos and need tests
2023-07-11 11:51:44 +02:00
Takacs, Philipp
716c8f1c4c handle snapshots over context_save context_restore 2023-07-11 11:51:44 +02:00
Takacs, Philipp
80bd825420 implement simple memory snapshot mechanismus
Uses Copy on Write to make it posible to restore the memory state after a snapshot
was made. To restore all MemoryRegions created after the snapshot are removed.
2023-07-11 11:51:40 +02:00
mio
aee4038526 Fix test_x86_0xff_lcall test 2023-07-07 18:50:55 +08:00
mio
2325f41ead Add a unit test for a7a5d187e7 2023-06-30 20:28:59 +08:00
Robert Xiao
b041345a73 Fix RISCV test_riscv32_fp_move test
RISCV FP registers are 64-bit in size, even in 32-bit mode, because they can
hold doubles. The test even uses the double-precision instruction fmv.d. Thus,
the reads should be reading 64-bit registers.
2023-06-16 15:23:43 -07:00
Robert Xiao
d7a806c026 Reformat code with format.sh 2023-06-16 15:23:41 -07:00
Takacs, Philipp
073c4b74ca load_helper only call cpu_loop_exit() when emulation is running
The load_helper is sometimes called from register writes. When the load
fails check if emulation is running before jump out of the emulated code.
2023-05-09 14:58:40 +02:00
Mio
bbbc7856ac Invalidate tb cache once mapping is removed 2023-04-12 20:56:54 +08:00
Takacs, Philipp
8b2c477578 clear the TLB cache in uc_ctl_flush_tlb
uc_ctl_flush_tlb implies that the tlb is flushed. This change adds
UC_CTL_TLB_FLUSH which clears the TLB and set the uc_ctl_flush_tlb
alias to UC_CTL_TLB_FLUSH. Also adds a uc_ctl_flush_tb alias for
UC_CTL_TB_FLUSH.
2023-03-28 14:11:41 +02:00
Takacs, Philipp
e96ac42b2e Remove MMU hacks
Unicorn has included some ugly hacks to provide a envirement where vaddr == paddr.
These hacks where to use the full 64 bit mappings on x86 without init the mmu
and some memory redirect for MIPS.

The UC_TLB_CPU mode defaults to vaddr == paddr, therfor these hacks aren't
required anymore.
2023-03-28 14:02:17 +02:00
Takacs, Philipp
e25419bb2d add virtuall tlb
this virtuall tlb allows to use mmu indipendent of the architectur
2023-03-28 13:50:11 +02:00
Takacs, Philipp
7f1eb4532d add basic mmu tests
Some simple tests for diffrent mmu.
Basicly add some tlb entries, enable the mmu try to read from virtual address

The aarm64 test was provided by imre-kis-arm in #1718
2023-03-28 13:50:11 +02:00
5e2074da6a Merge pull request #1808 from kallisti5/haiku-fix-2023
build: Fixes for Haiku
2023-03-26 12:17:23 +08:00
Alexander von Gluck IV
d504e3a004 build: Fixes for Haiku
* Haiku is fully posix, so can be lumped together with most unix cases
2023-03-22 13:58:10 -05:00
mio
11fcbad9ff Remove redundant printf 2023-03-12 20:28:01 +01:00
Takacs, Philipp
b7b1a4d6b4 difference between stop_request and quit_request
quit_request is for internal use. This means the IP register was updated and
qemu needs to rebuild the translation blocks.

stop_request is set by the user (uc_emu_stop) to indecate that unicorn sould
stop emulating.
2023-03-07 14:38:49 +01:00
mio
133504b504 Fix wrong IP in x86_16 because of cs_base not substracted 2023-02-20 20:21:56 +01:00
mio
e9c1c17f6d Fix endianess detection 2022-11-16 15:16:49 +01:00
mio
fc193ffe24 Fix missing macros 2022-10-28 17:55:39 +02:00
mio
a40bf26263 Disable test_x86_unaligned_access on be hosts 2022-10-28 17:53:20 +02:00
mio
428ed8fd21 Fix test_x86_unaligned_access for big endian hosts 2022-10-28 17:47:55 +02:00
mio
4b961a8ef6 Apply fix for big endian hosts per #1710 2022-10-28 16:20:20 +02:00
mio
47275c18f4 Fix a test bug 2022-10-28 15:02:59 +02:00
mio
d80cd54b0f Revert test_ctl endian changes 2022-10-27 23:39:43 +02:00
mio
bb7b5bb64a Use macro bswap 2022-10-27 23:32:15 +02:00
mio
e01556557e Fix endianess in test_ctl 2022-10-27 22:52:25 +02:00
mio
fb8fb1ca7a Add headers for endianess 2022-10-27 22:51:56 +02:00
mio
da3999b6f0 Add tests for thumb2 2022-10-21 11:37:07 +02:00
mio
3ea7857be3 Exit early when invalid read happens
In this way, the target register won't be overwritten
2022-10-20 21:57:28 +02:00