mothran
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d1e19df64e
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update the sparc_reg to test all g/o/l registers
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2015-09-14 23:05:33 -07:00 |
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mothran
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69d73aa845
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added emulated SPARC code for regress/sparc_reg.py, appears to be a bug in G and I registers
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2015-09-14 21:23:42 -07:00 |
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mothran
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6b521e9e9b
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update the sparc reg read/write to include o/l/i registers
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2015-09-14 20:03:32 -07:00 |
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Nguyen Anh Quynh
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548355acca
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sparc: do not accept BIGENDIAN mode in samples. more sanity check should be done in the core
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2015-09-11 14:02:27 +08:00 |
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Nguyen Anh Quynh
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1724fabb05
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add shebang for regress/sparc_reg.py
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2015-09-08 09:14:22 +08:00 |
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Ryan Hileman
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5f6c475479
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add regress for #126
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2015-09-07 18:08:05 -07:00 |
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