Takacs, Philipp
e96ac42b2e
Remove MMU hacks
...
Unicorn has included some ugly hacks to provide a envirement where vaddr == paddr.
These hacks where to use the full 64 bit mappings on x86 without init the mmu
and some memory redirect for MIPS.
The UC_TLB_CPU mode defaults to vaddr == paddr, therfor these hacks aren't
required anymore.
2023-03-28 14:02:17 +02:00
Takacs, Philipp
e25419bb2d
add virtuall tlb
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this virtuall tlb allows to use mmu indipendent of the architectur
2023-03-28 13:50:11 +02:00
Takacs, Philipp
901034577a
i386 call internal helper on special porpese register write
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Some registers writes have side effects. i.e. write to cr3 flush the tlb,
if the PG bit is set.
2023-03-28 13:50:11 +02:00
Takacs, Philipp
f2eb1f4711
i386 mmu hack: Allow emulate usermode without mmu
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This basicaly mappes virtual addresses to physical addresses 1:1 when
the mmu is disabled in the cpu. So you can use the full 64 bit addressspace
without required to configure the mmu.
2023-03-28 13:50:11 +02:00
Takacs, Philipp
b7b1a4d6b4
difference between stop_request and quit_request
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quit_request is for internal use. This means the IP register was updated and
qemu needs to rebuild the translation blocks.
stop_request is set by the user (uc_emu_stop) to indecate that unicorn sould
stop emulating.
2023-03-07 14:38:49 +01:00
Takacs, Philipp
14404ef04b
[x86] don't hardcode cpuid results
...
The cpuid results are set by the selected cpu.
CLOSES #1787
2023-02-27 12:34:38 +01:00
133504b504
Fix wrong IP in x86_16 because of cs_base not substracted
2023-02-20 20:21:56 +01:00
Nguyen Anh Quynh
9dc001d686
remove unused code in PPC & dis-asm.h
2022-12-07 01:36:44 +08:00
9c5358c759
Respect QEMU ZMM_Q to work on big endian hosts
2022-10-28 17:37:02 +02:00
6162708bb2
Hack more to support BE32
2022-10-21 11:30:22 +02:00
13b8e2625f
Check PC range for mem hooks
2022-10-20 21:25:21 +02:00
a5d4d30a31
Sync PC for mem ldst on aarch64
2022-10-20 21:19:18 +02:00
35010035d7
Fix macro typo
...
Thanks @roehling
2022-10-20 20:10:27 +02:00
TSR Berry
442dd437e1
aarch64: Move FPCR and FPSR registers to not break compatibility
...
Co-authored-by: merry <git@mary.rs >
2022-10-14 17:31:20 +02:00
TSR Berry
12fd4fc086
aarch64: Add FPCR and FPSR registers
...
Co-authored-by: merry <git@mary.rs >
2022-10-14 15:18:14 +02:00
19d8876e23
Deep copy for arm cpu state
2022-10-01 00:14:08 +02:00
5e060513a0
Merge pull request #1687 from relapids/clang_cl_support
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Allow building with clang-cl (using MSVC config) on Windows.
2022-09-27 23:02:21 +02:00
a0e119c6f0
Format code
2022-08-31 23:27:24 +08:00
a63002872f
Merge pull request #1688 from relapids/tricore_leak
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Fix memory leaks in TriCore target. (#1681 )
2022-08-31 22:07:10 +08:00
relapids
e15173dd26
Fix memory leaks in TriCore target.
2022-08-15 21:26:29 -07:00
relapids
a3ccbf2e59
Fix memory leak in PPC target.
2022-08-15 18:57:10 -07:00
relapids
2ac7b55797
Allow building with clang-cl on Windows.
2022-08-15 15:50:46 -07:00
ffb047fe37
Merge pull request #1668 from Yu3H0/fix_tricore_pc_problem
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fix issue 1663:tricore pc don't move
2022-07-26 22:08:43 +08:00
Yu3h0
ca6a8b4cac
fix issue 1663:tricore pc don't move
2022-07-26 13:41:13 +08:00
mio
6db6790ec2
Merge remote-tracking branch 'zachesez/ppc_cr_read_fix' into dev
2022-07-23 20:46:40 +08:00
Zach Szczesniak
2b25867e4b
Fixed endianness when writing PPC32 CR register.
2022-07-20 18:31:13 -04:00
Duncan Ogilvie
22ea31cdf7
Fail when VEX.L is set in SSE instructions (AVX is not supported)
...
Closes #1656
2022-07-20 13:48:31 +02:00
ba50035830
Format code
2022-05-23 12:30:44 +02:00
17fa839a56
Eliminate more warnings in s390x
2022-05-21 00:07:20 +02:00
82d1c9e925
Eliminate warnings
2022-05-21 00:02:29 +02:00
9167ab8671
Set riscv_get_pc for uc->get_pc
2022-05-21 00:02:22 +02:00
Ondřej Ondryáš
f3b776dd7d
Support reads and writes over all Arm SIMD registers
2022-05-20 00:30:11 +02:00
b827ebf4c3
Format code
2022-05-07 00:30:18 +02:00
345b63ee96
Only exit TB if pc is within the memory range
2022-05-07 00:16:31 +02:00
Eric Poole
cfee2139a0
TriCore Support ( #1568 )
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* TriCore Support
python sample
* Update sample_tricore.py
Correct attribution
* Update sample_tricore.py
Fixed byte code to execute properly.
* Update sample_tricore.py
Removed testing artifact
* Added tricore msvc config-file.h
* Added STATIC to tricore config and added helper methods to symbol file generation.
* Update op_helper.c
Use built in crc32
* Fix tricore samples and small code blocks are now handled properly
* Add CPU types
* Generate bindings
* Format code
Co-authored-by: lazymio <mio@lazym.io >
2022-04-29 23:11:34 +02:00
b136f08f2d
Check CPU model for uc_ctl
2022-04-16 17:49:47 +02:00
shuffle2
2912cd1e29
fix rust bindings build on windows ( #1584 )
...
Refine rust bindings.
2022-04-16 13:40:04 +02:00
e3d0a33ab8
Fix BE32 usermode address XOR
2022-04-05 11:55:58 +02:00
2f113b11d1
Fix symbol clash on bunlded static libs
2022-04-04 11:24:59 +02:00
Ilya Leoshkevich
7de130a5d7
s390x/tcg: Fix BRASL and BRCL with large negative offsets
...
This is a backport of the following upstream commits:
- commit fc3dd86a290a ("s390x/tcg: Fix BRASL with a large negative offset")
- commit 16ed5f14215b ("s390x/tcg: Fix BRCL with a large negative offset")
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com >
2022-03-17 14:23:57 +01:00
9f62c71094
Sync PC for SYS instruction hook
2022-02-27 15:30:27 +01:00
e5207a1363
Implement UC_HOOK_INSN for aarch64 MRS/MSR/SYS/SYSL
2022-02-27 15:28:31 +01:00
d946114dfe
Set EFLAGS correctly on startup
2022-02-25 22:44:42 +01:00
84e796494f
Format code
2022-02-25 22:24:25 +01:00
8d9ca1ce84
Format
2022-02-17 10:37:34 +01:00
27ef63cc8d
Add UC_PPC_REG_CR
2022-02-15 22:07:53 +01:00
e382ca102a
Fix the regression bug
2022-02-13 09:52:00 +01:00
05b9a021dc
Merge pull request #1453 from scribam/reg-read-write-fpscr
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unicorn_arm: add reg_read/write operations for FPSCR and FPSID
2022-02-13 09:02:32 +01:00
52e0963cc7
Backward compatibility to enable full 64bits address space
2022-02-12 22:54:21 +01:00
81eb7da837
Backward compatibility for c13_c0_3
2022-02-12 22:31:10 +01:00
