Takacs, Philipp
e96ac42b2e
Remove MMU hacks
...
Unicorn has included some ugly hacks to provide a envirement where vaddr == paddr.
These hacks where to use the full 64 bit mappings on x86 without init the mmu
and some memory redirect for MIPS.
The UC_TLB_CPU mode defaults to vaddr == paddr, therfor these hacks aren't
required anymore.
2023-03-28 14:02:17 +02:00
Takacs, Philipp
7f1eb4532d
add basic mmu tests
...
Some simple tests for diffrent mmu.
Basicly add some tlb entries, enable the mmu try to read from virtual address
The aarm64 test was provided by imre-kis-arm in #1718
2023-03-28 13:50:11 +02:00
ba50035830
Format code
2022-05-23 12:30:44 +02:00
dae48aecee
Mem hook should return a bool
2022-05-20 13:31:54 +02:00
Quentin DUCASSE
f569417878
Equivalent tests for riscv
2022-05-04 17:18:47 +02:00
shuffle2
2912cd1e29
fix rust bindings build on windows ( #1584 )
...
Refine rust bindings.
2022-04-16 13:40:04 +02:00
7bb0abb977
Format
2021-12-22 20:37:15 +01:00
Quentin DUCASSE
033e79abac
Added cache flush after code patching in unit tests for arm64 and riscv
2021-12-17 14:55:08 +01:00
Quentin DUCASSE
549274f44c
Code patching tests for riscv and arm64
2021-12-10 15:27:54 +01:00
907ec5095d
Fix a stackoverflow in tests
2021-11-21 19:28:45 +01:00
fc467edbc6
Fix 32bit target getting wrong offset for mmio
2021-11-16 22:40:57 +01:00
c6fdbb3735
Add RISCV CSR registers
2021-11-07 20:36:04 +01:00
67e2386da6
Add test and close #1477
2021-11-03 21:40:13 +01:00
58edb2abe7
Format
2021-11-03 13:28:12 +01:00
09aa0f944f
Merge QDucasse:riscv_extension_d
...
Fix and close #1469
Fix test for riscv float points
Fix the riscv cpu config we left out
2021-11-03 13:20:46 +01:00
e62b0ef255
Add clang-format and format code to qemu code style
2021-10-29 12:44:49 +02:00
Quentin DUCASSE
5fd90ca1ef
Added 3 steps unit test
2021-10-19 17:20:10 +02:00
Quentin DUCASSE
47f986fc93
Unit test POC for RISCV issue
2021-10-19 17:12:52 +02:00
Nguyen Anh Quynh
aaaea14214
import Unicorn2
2021-10-03 22:14:44 +08:00
