- Added fullMode input in workflow_dispatch
- Take decision whether to build either in debug or release mode and if to build for all python versions according to the commit message patterns
- Set proper artifact names
- Removed not needed steps
- Compacted some steps in order to leverage more the matrix feature
- Bumped cibuildwheel action to 2.22.0
- Run actual regress tests in place of sample scripts
- Specify optional test install in pyproject.toml with proper requirements
- Derive package version from git tags
- Add GENERATORS env var support in setup.py to specify cmake generator and minor refactoring
- Minor cleanup/refactoring for the regress test suite
- Marked some regress tests with skipIf to skip them in case of old python versions
- Marked some failing regress tests to be checked with skipIf
Unlike some other architectures, RISC-V does not expose the current
privilege mode in any architecturally-defined register. That is intentional
to make it easier to implement virtualization in software, but a Unicorn
caller operates outside of the emulated hart and so it can and should be
able to observe and change the current privilege mode in order to properly
emulate certain behaviors of a real CPU.
The current privilege level is therefore now exposed as a new
pseudo-register using the name "priv", which matches the name of the
virtual register used by RISC-V's debug extension to allow the debugger
to read and change the privilege mode while the hart is halted. Unicorn's
use of it is conceptually similar to a debugger.
The bit encoding of this register is the same as specified in RISC-V Debug
Specification v1.0-rc3 Section 4.10.1. It's defined as a "virtual"
register exposing a subset of fields from the dcsr register, although here
it's implemented directly inside the Unicorn code because QEMU doesn't
currently have explicit support for the CSRs from the debug specification.
If it supports "dcsr" in a future release then this implementation could
change to wrap reading and writing that CSR and then projecting the "prv"
and "v" bitfields into the correct locations for the virtual register.
* enable notdirty_write for snapshots when possible
Snapshots only happens when the priority of the memory region is smaller
then the snapshot_level. After a snapshot notdirty can be set.
* disable notdirty_write for self modifying code
When SMC access the memory region more then once the
tb must be rebuild multible times.
fixes#2029
* notdirty_write better hook check
Check all relevant memory hooks before enabling notdirty write.
This also checks if the memory hook is registered for the affected
region. So it is possible to use notdirty write and have some hooks
on different addresses.
* notdirty_write check for addr_write in snapshot case
* self modifying code clear recursive mem access
when self modifying code does unaligned memory accese sometimes
uc->size_recur_mem is changed but for notdirty write not changed back.
This causes mem_hooks to be missed. To fix this uc->size_recur_mem is
set to 0 before each cpu_exec() call.
* optimize ram block handling
Save the last element of the ram_list. This allows to
faster find where to add new elements when they are not
bigger then page size.
* save ram_list freed
this keeps the optimization for find_ram_offset() intact after snapshot
restore.
* cow only clear the tlb of affected pages
* update flatview when possible
Building each flatview new when the memory has changed is quite
expensive when many MemoryRegions are used. This is an issue when using
snapshots.
* update benchmark for new api
* save flatview in context
this avoids rebuilding the flatview when restore a context.
* init context flatview with zero
* address_space_dispatch_clear remove subpage with higher priority
* docutemnt the options for UC_CTL_CONTEXT_MODE
Specialy stress that with UC_CTL_CONTEXT_MEMORY it is not possible to
use the context with a different unicorn object.
* Styling and commets fixes
* Add errno API support
* Improve OOP approach by adjusting the way reg types are selected
* Leverage new approach to deduplicate reg_read and reg_write code
* Adjust reg_read_batch
* Add support for reg_write_batch
* Adjust x86 MSR accessors
* Turn asserts into descriptive exceptions
* Improve comments and styling
* Fix ARM memcpy neon regression test
* Modify canonicals import
* Introduce ARM CP reg accessors
* Add a quick test helper macro to test_x86.c
* Add regression tests for bswap and rex prefixes
* Properly ignore REX prefixes when appropriate
* Fix bswap ax emulator detection
uc->target_page_align is a uint32_t. When the binary not will only
invert the 32 bit of the value. Used this in a binary and operator with
a uint64_t will case the upper 32bit of the address to be 0. Therefor
the bug only appears when the upper 32bit of the address are used.
Now a local uint64_t variable is used for the alignemend and the test
uses a not page alligned address which does not fit in 32bit.
Access to TB, DEC registers was lead to crash
spr_read_decr and others are changed to spr_read_generic
spr_write_decr and others are changed to spr_write_generic
Uses Copy on Write to make it posible to restore the memory state after a snapshot
was made. To restore all MemoryRegions created after the snapshot are removed.
RISCV FP registers are 64-bit in size, even in 32-bit mode, because they can
hold doubles. The test even uses the double-precision instruction fmv.d. Thus,
the reads should be reading 64-bit registers.
uc_ctl_flush_tlb implies that the tlb is flushed. This change adds
UC_CTL_TLB_FLUSH which clears the TLB and set the uc_ctl_flush_tlb
alias to UC_CTL_TLB_FLUSH. Also adds a uc_ctl_flush_tb alias for
UC_CTL_TB_FLUSH.
Unicorn has included some ugly hacks to provide a envirement where vaddr == paddr.
These hacks where to use the full 64 bit mappings on x86 without init the mmu
and some memory redirect for MIPS.
The UC_TLB_CPU mode defaults to vaddr == paddr, therfor these hacks aren't
required anymore.
