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ea9c7425b0
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Fix the wrong PC when arm translation fectches unmapped memory
This behavior keeps the same with Unicorn1, though, different from arm doc
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2022-01-16 16:42:38 +01:00 |
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459a595a98
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Merge branch 'dev' into s390x
Mostly for bindings update.
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2022-01-15 20:56:39 +01:00 |
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6ed2214399
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Rebuilt hflags when swithing modes
Or we may get the wrong mode during translation
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2022-01-14 19:37:48 +01:00 |
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33afdcf872
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Save CC at the end of emulation
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2022-01-10 21:48:03 +01:00 |
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9ac796531a
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Don't cache S390SkeyState and S390SkeysClass
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2022-01-10 19:18:52 +01:00 |
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980eae7f44
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Sync PC at the end of emulation
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2022-01-10 15:45:56 +01:00 |
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441afe17e6
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Add psw.mask register
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2022-01-10 15:34:04 +01:00 |
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71f044ca50
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Merge branch 'dev' into s390x
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2022-01-10 15:17:42 +01:00 |
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36afa1022c
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More PPC registers
Add FPR0-31, CR0-7, LR, CTR, MSR, XER, FPSCR for PPC
Add a test for ppc32 float point
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2022-01-10 15:16:10 +01:00 |
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8ad9f8ecb1
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This reverts Hack 05ba21160619724033ec83469bbb66bda9e3f5fb and applies the correct fix
And enable experimental v8 support for arm max cpu
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2022-01-05 21:58:40 +01:00 |
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c3a49766d8
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Fix #1522
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2022-01-05 20:02:41 +01:00 |
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7a886f59df
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Fix #1525
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2022-01-05 19:38:22 +01:00 |
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d854e22301
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Add x87 FPU registers #1524
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2022-01-04 21:12:12 +01:00 |
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47097b55b7
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Fix #1520
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2022-01-04 21:01:20 +01:00 |
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scribam
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039cd50187
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unicorn_arm: add reg_read/write operations for FPSCR and FPSID
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2022-01-04 11:36:06 +01:00 |
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Nguyen Anh Quynh
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e55b76f057
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s390x: cleanup & re-enable some skey code
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2021-12-31 10:05:05 +08:00 |
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Nguyen Anh Quynh
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1a0f0d0768
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s390x: remove some unused fields in S390CPU
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2021-12-31 09:48:16 +08:00 |
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a06563ecdd
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Fix memory leak
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2021-12-31 00:24:18 +01:00 |
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3b667338cf
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Fix s390x warnings
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2021-12-31 00:10:50 +01:00 |
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085ee07c73
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No more hard-coded cpu models
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2021-12-30 01:05:10 +01:00 |
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fdbd743c21
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Remove hard-coded cpu model
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2021-12-30 00:54:55 +01:00 |
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a72cbda6de
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Initialize empty structs explictly to build on MSVC
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2021-12-30 00:51:07 +01:00 |
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03f9dd8b61
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Expand case ranges to build on MSVC
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2021-12-30 00:42:13 +01:00 |
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ab4ef2e1de
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Fix MSVC build and remove warning about unused functions
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2021-12-30 00:26:25 +01:00 |
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034a1aa5f2
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Make s390x stopping mechanism work
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2021-12-27 23:48:20 +01:00 |
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a38151bf77
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Make s390x skey work
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2021-12-27 23:19:17 +01:00 |
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e977f81813
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Make s390x build
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2021-12-26 23:09:25 +01:00 |
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faa689c0f0
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Merge systemz to the latest uc2 codebase
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2021-12-26 22:58:32 +01:00 |
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cddc9cf2ed
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Fix arm post init
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2021-12-25 00:16:51 +01:00 |
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4f73d75ea8
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Fix #1500
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2021-12-23 21:46:27 +01:00 |
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ef6f8a2427
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Fix x86 CPUID
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2021-12-22 23:39:41 +01:00 |
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7bb756249a
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Better design of cpuid instruction hook
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2021-12-22 20:36:56 +01:00 |
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Nguyen Anh Quynh
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09b0c66f11
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move all static vars in translate.c to tcg.h
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2021-12-07 04:53:32 +08:00 |
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Nguyen Anh Quynh
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b042a6a01d
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add missing files
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2021-12-06 04:28:13 +08:00 |
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8a0ca8715e
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Fix SR read/write and a test
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2021-12-04 23:22:28 +01:00 |
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Brandon Miller
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d204dc6374
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Added SR to M68K reg_read and reg_write (#1507)
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2021-12-02 14:12:49 +08:00 |
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221cde18df
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Write CPSR as it is initiated from instructions to allow regs switch
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2021-11-24 17:10:51 +01:00 |
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87a391d549
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Inline uc_tracecode when there is only exactly one hook
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2021-11-21 16:44:39 +01:00 |
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23ef5da491
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Merge pull request #1481 from bet4it/cp15
Restore cp15 registers
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2021-11-09 16:50:31 +01:00 |
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Bet4
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acaed986b5
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Restore cp15 registers
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2021-11-09 13:13:08 +08:00 |
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640251e1aa
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Leave out size parameter in callback
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2021-11-09 00:21:34 +01:00 |
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c6fdbb3735
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Add RISCV CSR registers
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2021-11-07 20:36:04 +01:00 |
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George Hotz
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7268c2a19b
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mips: support reading and writing of hi/lo regs
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2021-11-07 20:27:02 +01:00 |
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613ddf0985
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Format
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2021-11-04 19:58:44 +01:00 |
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871de4ad65
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Split mips cpu to 32 and 64
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2021-11-04 19:58:32 +01:00 |
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0555095388
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Support changing cpu model for ppc
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2021-11-04 19:53:02 +01:00 |
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e5a2eae173
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Add comment for default cpu model
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2021-11-04 19:22:50 +01:00 |
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64452e249d
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Support changing cpu model for sparc
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2021-11-04 19:22:08 +01:00 |
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b0280f5e55
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Support changing cpu model for m68k
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2021-11-04 19:16:35 +01:00 |
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172a2fbe6d
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Support changing cpu model for riscv
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2021-11-04 19:13:53 +01:00 |
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