3 Commits

Author	SHA1	Message	Date
Robert Xiao	30d202b89e	Simplify reg_read/reg_write, obtaining a perf boost. ... Single reg_read/reg_write is now about 25% faster.	2023-06-16 15:23:42 -07:00
Robert Xiao	4055a5ab10	Implement uc_reg_{read,write}{,_batch}2 APIs. ... These APIs take size parameters, which can be used to properly bounds-check the inputs and outputs for various registers. Additionally, all backends now throw UC_ERR_ARG if the input register numbers are invalid. Completes #1831.	2023-06-16 15:23:42 -07:00
Eric Poole	cfee2139a0	TriCore Support (#1568) ... * TriCore Support python sample * Update sample_tricore.py Correct attribution * Update sample_tricore.py Fixed byte code to execute properly. * Update sample_tricore.py Removed testing artifact * Added tricore msvc config-file.h * Added STATIC to tricore config and added helper methods to symbol file generation. * Update op_helper.c Use built in crc32 * Fix tricore samples and small code blocks are now handled properly * Add CPU types * Generate bindings * Format code Co-authored-by: lazymio <mio@lazym.io>	2022-04-29 23:11:34 +02:00