Nguyen Anh Quynh
c136b6b2bf
fix some compiler warnings
2024-04-22 20:03:07 +08:00
24f898fb58
Fix #1869
2024-02-15 15:22:32 +08:00
a6fb2a6870
Save jit state before/after callback
2024-02-13 11:13:01 +08:00
3c64e9a9e7
Revert previous wrong fixes
2024-01-03 18:06:09 +08:00
02e3cba4c4
HAVE_ATOMIC128 is defined as a number
2024-01-03 17:45:04 +08:00
3cff3eb2d5
Don't rely on dead code elimination
2024-01-03 16:50:28 +08:00
dotcirill
b0ea433772
Fix PPC32 fault when timer-spr access
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Access to TB, DEC registers was lead to crash
spr_read_decr and others are changed to spr_read_generic
spr_write_decr and others are changed to spr_write_generic
2023-12-06 01:58:50 +03:00
StalkR
db63f2d9d7
qemu: fix UBSAN errors in tcg and arm translation
2023-11-14 10:23:50 +01:00
Dimitris Glynos
9d8e639c69
fix fxsave fpip value, provide tests
2023-10-26 08:42:58 +03:00
c889258d8e
Avoid overwriting tmp0
2023-08-06 21:25:37 +08:00
basavesh
cf5e75953d
Backport qemu/qemu@75b208c
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target/i386: fix operand order for PDEP and PEXT
For PDEP and PEXT, the mask is provided in the memory (mod+r/m)
operand, and therefore is loaded in s->T0 by gen_ldst_modrm.
The source is provided in the second source operand (VEX.vvvv)
and therefore is loaded in s->T1. Fix the order in which
they are passed to the helpers.
2023-08-03 13:12:39 +02:00
a7a5d187e7
Backport 10b8eb94c0
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target/i386: Verify memory operand for lcall and ljmp
These two opcodes only allow a memory operand.
Lacking the check for a register operand, we used the A0 temp
without initialization, which led to a tcg abort.
2023-06-30 20:21:56 +08:00
75676eb0cd
Also rebuild flags for aarch32
2023-06-28 10:39:25 +08:00
Robert Xiao
30d202b89e
Simplify reg_read/reg_write, obtaining a perf boost.
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Single reg_read/reg_write is now about 25% faster.
2023-06-16 15:23:42 -07:00
Robert Xiao
074566cf69
Slight refactoring to reduce code duplication.
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This also comes with a performance bump due to inlining of reg_read/reg_write
(as they're only called once now) and the unlikely() on CHECK_REG_TYPE.
2023-06-16 15:23:42 -07:00
Robert Xiao
4055a5ab10
Implement uc_reg_{read,write}{,_batch}2 APIs.
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These APIs take size parameters, which can be used to properly bounds-check the
inputs and outputs for various registers. Additionally, all backends now throw
UC_ERR_ARG if the input register numbers are invalid.
Completes #1831 .
2023-06-16 15:23:42 -07:00
Robert Xiao
d7a806c026
Reformat code with format.sh
2023-06-16 15:23:41 -07:00
a24e53d794
Rebuild flags after writing to cp registers
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This is buggy as this momemt per https://github.com/unicorn-engine/unicorn/issues/1789#issuecomment-1546807410
We need either doc this or save more information for a context
2023-05-14 13:35:31 +02:00
Takacs, Philipp
e96ac42b2e
Remove MMU hacks
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Unicorn has included some ugly hacks to provide a envirement where vaddr == paddr.
These hacks where to use the full 64 bit mappings on x86 without init the mmu
and some memory redirect for MIPS.
The UC_TLB_CPU mode defaults to vaddr == paddr, therfor these hacks aren't
required anymore.
2023-03-28 14:02:17 +02:00
Takacs, Philipp
e25419bb2d
add virtuall tlb
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this virtuall tlb allows to use mmu indipendent of the architectur
2023-03-28 13:50:11 +02:00
Takacs, Philipp
901034577a
i386 call internal helper on special porpese register write
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Some registers writes have side effects. i.e. write to cr3 flush the tlb,
if the PG bit is set.
2023-03-28 13:50:11 +02:00
Takacs, Philipp
f2eb1f4711
i386 mmu hack: Allow emulate usermode without mmu
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This basicaly mappes virtual addresses to physical addresses 1:1 when
the mmu is disabled in the cpu. So you can use the full 64 bit addressspace
without required to configure the mmu.
2023-03-28 13:50:11 +02:00
Takacs, Philipp
b7b1a4d6b4
difference between stop_request and quit_request
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quit_request is for internal use. This means the IP register was updated and
qemu needs to rebuild the translation blocks.
stop_request is set by the user (uc_emu_stop) to indecate that unicorn sould
stop emulating.
2023-03-07 14:38:49 +01:00
Takacs, Philipp
14404ef04b
[x86] don't hardcode cpuid results
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The cpuid results are set by the selected cpu.
CLOSES #1787
2023-02-27 12:34:38 +01:00
133504b504
Fix wrong IP in x86_16 because of cs_base not substracted
2023-02-20 20:21:56 +01:00
Nguyen Anh Quynh
9dc001d686
remove unused code in PPC & dis-asm.h
2022-12-07 01:36:44 +08:00
9c5358c759
Respect QEMU ZMM_Q to work on big endian hosts
2022-10-28 17:37:02 +02:00
6162708bb2
Hack more to support BE32
2022-10-21 11:30:22 +02:00
13b8e2625f
Check PC range for mem hooks
2022-10-20 21:25:21 +02:00
a5d4d30a31
Sync PC for mem ldst on aarch64
2022-10-20 21:19:18 +02:00
35010035d7
Fix macro typo
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Thanks @roehling
2022-10-20 20:10:27 +02:00
TSR Berry
442dd437e1
aarch64: Move FPCR and FPSR registers to not break compatibility
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Co-authored-by: merry <git@mary.rs >
2022-10-14 17:31:20 +02:00
TSR Berry
12fd4fc086
aarch64: Add FPCR and FPSR registers
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Co-authored-by: merry <git@mary.rs >
2022-10-14 15:18:14 +02:00
19d8876e23
Deep copy for arm cpu state
2022-10-01 00:14:08 +02:00
5e060513a0
Merge pull request #1687 from relapids/clang_cl_support
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Allow building with clang-cl (using MSVC config) on Windows.
2022-09-27 23:02:21 +02:00
a0e119c6f0
Format code
2022-08-31 23:27:24 +08:00
a63002872f
Merge pull request #1688 from relapids/tricore_leak
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Fix memory leaks in TriCore target. (#1681 )
2022-08-31 22:07:10 +08:00
relapids
e15173dd26
Fix memory leaks in TriCore target.
2022-08-15 21:26:29 -07:00
relapids
a3ccbf2e59
Fix memory leak in PPC target.
2022-08-15 18:57:10 -07:00
relapids
2ac7b55797
Allow building with clang-cl on Windows.
2022-08-15 15:50:46 -07:00
ffb047fe37
Merge pull request #1668 from Yu3H0/fix_tricore_pc_problem
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fix issue 1663:tricore pc don't move
2022-07-26 22:08:43 +08:00
Yu3h0
ca6a8b4cac
fix issue 1663:tricore pc don't move
2022-07-26 13:41:13 +08:00
mio
6db6790ec2
Merge remote-tracking branch 'zachesez/ppc_cr_read_fix' into dev
2022-07-23 20:46:40 +08:00
Zach Szczesniak
2b25867e4b
Fixed endianness when writing PPC32 CR register.
2022-07-20 18:31:13 -04:00
Duncan Ogilvie
22ea31cdf7
Fail when VEX.L is set in SSE instructions (AVX is not supported)
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Closes #1656
2022-07-20 13:48:31 +02:00
ba50035830
Format code
2022-05-23 12:30:44 +02:00
17fa839a56
Eliminate more warnings in s390x
2022-05-21 00:07:20 +02:00
82d1c9e925
Eliminate warnings
2022-05-21 00:02:29 +02:00
9167ab8671
Set riscv_get_pc for uc->get_pc
2022-05-21 00:02:22 +02:00
Ondřej Ondryáš
f3b776dd7d
Support reads and writes over all Arm SIMD registers
2022-05-20 00:30:11 +02:00
