Commit Graph

829 Commits

Author SHA1 Message Date
Jose Martins
58f1a612e8 target/riscv: fix wfi exception behavior
The wfi exception trigger behavior should take into account user mode,
hstatus.vtw, and the fact the an wfi might raise different types of
exceptions depending on various factors:

If supervisor mode is not present:

- an illegal instruction exception should be generated if user mode
executes and wfi instruction and mstatus.tw = 1.

If supervisor mode is present:

- when a wfi instruction is executed, an illegal exception should be triggered
if either the current mode is user or the mode is supervisor and mstatus.tw is
set.

Plus, if the hypervisor extensions are enabled:

- a virtual instruction exception should be raised when a wfi is executed from
virtual-user or virtual-supervisor and hstatus.vtw is set.

Signed-off-by: Jose Martins <josemartins90@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210420213656.85148-1-josemartins90@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-09-03 13:44:55 -07:00
Duncan Ogilvie
87610baa3f Fix emulator detection (#1966)
* Add a quick test helper macro to test_x86.c

* Add regression tests for bswap and rex prefixes

* Properly ignore REX prefixes when appropriate

* Fix bswap ax emulator detection
2024-07-19 11:11:21 +08:00
BitMaskMixer
8e6499fb0b gcc compiler warning fixes (#1977)
* fix for enum-int-mismatch

* fix for unused-variable
2024-07-19 11:09:57 +08:00
Nguyen Anh Quynh
751a4d0f03 compile warning: remove some unused vars 2024-05-02 16:26:41 +08:00
Nguyen Anh Quynh
c136b6b2bf fix some compiler warnings 2024-04-22 20:03:07 +08:00
mio
e03109d8c9 Respect users' decision for UC_ERR_INSN_INVALID 2024-03-08 17:31:27 +08:00
mio
24f898fb58 Fix #1869 2024-02-15 15:22:32 +08:00
8a1c8daca3 Add a comment 2024-02-13 19:11:22 +08:00
71c729a9d7 Define HAVE_SPRR 2024-02-13 19:09:35 +08:00
4245475514 Detect if we have valid pthread_jit_write_protect_np 2024-02-13 16:21:53 +08:00
b31081a105 Remove unused var 2024-02-13 14:38:48 +08:00
78ea3c8301 Fix m1 defines 2024-02-13 11:52:10 +08:00
a4ba7c9dd5 Add inline 2024-02-13 11:48:24 +08:00
591b562721 Fix defined 2024-02-13 11:38:49 +08:00
a6fb2a6870 Save jit state before/after callback 2024-02-13 11:13:01 +08:00
822bb527f3 M1 W^X fully supported 2024-02-12 00:10:44 +08:00
redoste
a070ea95af Backport qemu/qemu@852f933
tcg: Fix do_nonatomic_op_* vs signed operations

The smin/smax/umin/umax operations require the operands to be
properly sign extended.  Do not drop the MO_SIGN bit from the
load, and additionally extend the val input.
2024-01-24 23:41:30 +01:00
Takacs, Philipp
8d3bf02041 fix cow when using uc_mem_write
memory_cow expect the address and size to be aligned on pagesize.
2024-01-10 15:54:46 +01:00
mio
e0eeda2362 Add arm for bad assert implementation 2024-01-03 18:07:04 +08:00
mio
3c64e9a9e7 Revert previous wrong fixes 2024-01-03 18:06:09 +08:00
mio
02e3cba4c4 HAVE_ATOMIC128 is defined as a number 2024-01-03 17:45:04 +08:00
mio
3cff3eb2d5 Don't rely on dead code elimination 2024-01-03 16:50:28 +08:00
dotcirill
b0ea433772 Fix PPC32 fault when timer-spr access
Access to TB, DEC registers was lead to crash
spr_read_decr and others are changed to spr_read_generic
spr_write_decr and others are changed to spr_write_generic
2023-12-06 01:58:50 +03:00
StalkR
db63f2d9d7 qemu: fix UBSAN errors in tcg and arm translation 2023-11-14 10:23:50 +01:00
Dimitris Glynos
9d8e639c69 fix fxsave fpip value, provide tests 2023-10-26 08:42:58 +03:00
Mario Haustein
9a2583e967 fix deprecated storage-class declarations 2023-10-08 13:40:23 +02:00
Mark Giraud
e189e1fb8b fix: Use correct addresses during memory cow 2023-08-23 10:18:42 +02:00
c889258d8e Avoid overwriting tmp0 2023-08-06 21:25:37 +08:00
basavesh
cf5e75953d Backport qemu/qemu@75b208c
target/i386: fix operand order for PDEP and PEXT

For PDEP and PEXT, the mask is provided in the memory (mod+r/m)
operand, and therefore is loaded in s->T0 by gen_ldst_modrm.
The source is provided in the second source operand (VEX.vvvv)
and therefore is loaded in s->T1. Fix the order in which
they are passed to the helpers.
2023-08-03 13:12:39 +02:00
6e97e59f54 Fix building on Apple Sillicon 2023-08-03 13:17:26 +08:00
Takacs, Philipp
f6cfe1092b vtlb only cache access permisions required for the operation
see #1845
2023-07-17 12:54:38 +02:00
Takacs, Philipp
df18756234 implement uc_mem_unmap with snapshots
still has todos and need tests
2023-07-11 11:51:44 +02:00
Takacs, Philipp
e54cf7ee03 find_ram_offset optimization
The ram_offset allocator searches the smalest gap in the ram_offset address space.
This is slow especialy in combination with many allocation (i.e. snapshots). When
it is known that there is no gap, this is now optimized.
2023-07-11 11:51:44 +02:00
Takacs, Philipp
80bd825420 implement simple memory snapshot mechanismus
Uses Copy on Write to make it posible to restore the memory state after a snapshot
was made. To restore all MemoryRegions created after the snapshot are removed.
2023-07-11 11:51:40 +02:00
Takacs, Philipp
065af19dc5 use address_space_translate to find memory mapping
first version has bugs
2023-07-11 11:47:50 +02:00
Takacs, Philipp
cd85f589a2 add memory_region_add_subregion_overlap 2023-07-11 11:47:50 +02:00
mio
a7a5d187e7 Backport 10b8eb94c0
target/i386: Verify memory operand for lcall and ljmp

These two opcodes only allow a memory operand.

Lacking the check for a register operand, we used the A0 temp

without initialization, which led to a tcg abort.
2023-06-30 20:21:56 +08:00
mio
75676eb0cd Also rebuild flags for aarch32 2023-06-28 10:39:25 +08:00
Robert Xiao
2b80ab425b Return new UC_ERR_OVERFLOW instead of UC_ERR_NOMEM when reg buffer is too small 2023-06-16 15:30:59 -07:00
Robert Xiao
30d202b89e Simplify reg_read/reg_write, obtaining a perf boost.
Single reg_read/reg_write is now about 25% faster.
2023-06-16 15:23:42 -07:00
Robert Xiao
074566cf69 Slight refactoring to reduce code duplication.
This also comes with a performance bump due to inlining of reg_read/reg_write
(as they're only called once now) and the unlikely() on CHECK_REG_TYPE.
2023-06-16 15:23:42 -07:00
Robert Xiao
4055a5ab10 Implement uc_reg_{read,write}{,_batch}2 APIs.
These APIs take size parameters, which can be used to properly bounds-check the
inputs and outputs for various registers. Additionally, all backends now throw
UC_ERR_ARG if the input register numbers are invalid.

Completes #1831.
2023-06-16 15:23:42 -07:00
Robert Xiao
d7a806c026 Reformat code with format.sh 2023-06-16 15:23:41 -07:00
mio
fa1f26138e Fix missing stdint
Co-authored-by: ζeh Matt <5415177+ZehMatt@users.noreply.github.com>
2023-06-10 23:48:18 +02:00
mio
49ccbde2d0 Leave out essential files
Co-authored-by: ζeh Matt <5415177+ZehMatt@users.noreply.github.com>
2023-06-10 23:44:05 +02:00
mio
8dffbc159c Add uc_ctl_get/set_tcg_buffer_size
We still need this API because the virtual memory address space of

32 bits os is only 4GB and we default need 1G per instance

Credits to @ZehMatt for original idea

Co-authored-by: ζeh Matt <5415177+ZehMatt@users.noreply.github.com>
2023-06-10 23:36:02 +02:00
mio
f8c7969d65 Revert "Add uc_ctl_get/set_tcg_buffer_size"
This reverts commit 3145e3c426 because not
properly co-authoer-ed.
2023-06-10 23:29:56 +02:00
mio
3145e3c426 Add uc_ctl_get/set_tcg_buffer_size 2023-06-10 16:08:29 +02:00
mio
5057f9925b Fix typo 2023-06-10 15:26:29 +02:00
mio
9de80cb625 Correct calling convention 2023-06-10 15:03:59 +02:00