Commit Graph

38 Commits

Author SHA1 Message Date
mio
791557e404 CI(full),CI(release): Should use if instead of ifdef 2025-02-11 17:44:24 +08:00
mio
b4eb933ec8 CI(full),CI(release): Do not refer to ATOMIC128 symbols if not available 2025-02-11 16:24:49 +08:00
Shivam7-1
ada8091ccc Fix heap buffer overflow in op_cksm function (#2096)
* Fix heap-buffer-overflow in op_cksm function

* Update header
2025-02-10 14:57:08 +08:00
0c512f91a1 Fix #1643
This adds an extra op to translator to allow the block hook sync pc in the very begining
2025-01-18 15:07:22 +08:00
mio
c42cc0fe86 More 16-bits aligned cpu state targets 2024-10-17 16:33:59 +08:00
mio
ffeddd7579 use qemu_memalign for all cpu structs
Some structs, specically CPUARMState is 16-bytes aligned.

This causes segment fault because gcc tends to vectorize

the assignment of the struct with infamous movaps tricks.

Without this patch, we fail on manylinux with 2.17 glibc

in release mode in i686.

qemu_memalign will ensure the alignment across platforms.
2024-10-17 13:50:07 +08:00
mio
9f935f505e Revert previous break changes that return UC_ERR_ARG for non-existing registers
But print a warning instead
2024-10-02 16:03:58 +08:00
Robert Xiao
30d202b89e Simplify reg_read/reg_write, obtaining a perf boost.
Single reg_read/reg_write is now about 25% faster.
2023-06-16 15:23:42 -07:00
Robert Xiao
074566cf69 Slight refactoring to reduce code duplication.
This also comes with a performance bump due to inlining of reg_read/reg_write
(as they're only called once now) and the unlikely() on CHECK_REG_TYPE.
2023-06-16 15:23:42 -07:00
Robert Xiao
4055a5ab10 Implement uc_reg_{read,write}{,_batch}2 APIs.
These APIs take size parameters, which can be used to properly bounds-check the
inputs and outputs for various registers. Additionally, all backends now throw
UC_ERR_ARG if the input register numbers are invalid.

Completes #1831.
2023-06-16 15:23:42 -07:00
Takacs, Philipp
e96ac42b2e Remove MMU hacks
Unicorn has included some ugly hacks to provide a envirement where vaddr == paddr.
These hacks where to use the full 64 bit mappings on x86 without init the mmu
and some memory redirect for MIPS.

The UC_TLB_CPU mode defaults to vaddr == paddr, therfor these hacks aren't
required anymore.
2023-03-28 14:02:17 +02:00
Takacs, Philipp
e25419bb2d add virtuall tlb
this virtuall tlb allows to use mmu indipendent of the architectur
2023-03-28 13:50:11 +02:00
Takacs, Philipp
b7b1a4d6b4 difference between stop_request and quit_request
quit_request is for internal use. This means the IP register was updated and
qemu needs to rebuild the translation blocks.

stop_request is set by the user (uc_emu_stop) to indecate that unicorn sould
stop emulating.
2023-03-07 14:38:49 +01:00
17fa839a56 Eliminate more warnings in s390x 2022-05-21 00:07:20 +02:00
82d1c9e925 Eliminate warnings 2022-05-21 00:02:29 +02:00
345b63ee96 Only exit TB if pc is within the memory range 2022-05-07 00:16:31 +02:00
shuffle2
2912cd1e29 fix rust bindings build on windows (#1584)
Refine rust bindings.
2022-04-16 13:40:04 +02:00
2f113b11d1 Fix symbol clash on bunlded static libs 2022-04-04 11:24:59 +02:00
Ilya Leoshkevich
7de130a5d7 s390x/tcg: Fix BRASL and BRCL with large negative offsets
This is a backport of the following upstream commits:
- commit fc3dd86a290a ("s390x/tcg: Fix BRASL with a large negative offset")
- commit 16ed5f14215b ("s390x/tcg: Fix BRCL with a large negative offset")

Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
2022-03-17 14:23:57 +01:00
Ilya Leoshkevich
ad984b9366 s390x TCG shift instruction fixes
Cherry-pick the following upstream commits:

521130f267 target/s390x: Fix SLDA sign bit index
57556b28af target/s390x: Fix SRDA CC calculation
df103c09bc target/s390x: Fix cc_calc_sla_64() missing overflows
6da170beda target/s390x: Fix shifting 32-bit values for more than 31 bits
2022-01-27 13:15:54 +01:00
33afdcf872 Save CC at the end of emulation 2022-01-10 21:48:03 +01:00
9ac796531a Don't cache S390SkeyState and S390SkeysClass 2022-01-10 19:18:52 +01:00
980eae7f44 Sync PC at the end of emulation 2022-01-10 15:45:56 +01:00
441afe17e6 Add psw.mask register 2022-01-10 15:34:04 +01:00
Nguyen Anh Quynh
e55b76f057 s390x: cleanup & re-enable some skey code 2021-12-31 10:05:05 +08:00
Nguyen Anh Quynh
1a0f0d0768 s390x: remove some unused fields in S390CPU 2021-12-31 09:48:16 +08:00
a06563ecdd Fix memory leak 2021-12-31 00:24:18 +01:00
3b667338cf Fix s390x warnings 2021-12-31 00:10:50 +01:00
mio
fdbd743c21 Remove hard-coded cpu model 2021-12-30 00:54:55 +01:00
mio
a72cbda6de Initialize empty structs explictly to build on MSVC 2021-12-30 00:51:07 +01:00
mio
03f9dd8b61 Expand case ranges to build on MSVC 2021-12-30 00:42:13 +01:00
mio
ab4ef2e1de Fix MSVC build and remove warning about unused functions 2021-12-30 00:26:25 +01:00
mio
034a1aa5f2 Make s390x stopping mechanism work 2021-12-27 23:48:20 +01:00
mio
a38151bf77 Make s390x skey work 2021-12-27 23:19:17 +01:00
mio
e977f81813 Make s390x build 2021-12-26 23:09:25 +01:00
mio
faa689c0f0 Merge systemz to the latest uc2 codebase 2021-12-26 22:58:32 +01:00
Nguyen Anh Quynh
09b0c66f11 move all static vars in translate.c to tcg.h 2021-12-07 04:53:32 +08:00
Nguyen Anh Quynh
b042a6a01d add missing files 2021-12-06 04:28:13 +08:00