6 Commits

Author	SHA1	Message	Date
lazymio	9167ab8671	Set riscv_get_pc for uc->get_pc	2022-05-21 00:02:22 +02:00
lazymio	345b63ee96	Only exit TB if pc is within the memory range	2022-05-07 00:16:31 +02:00
lazymio	c6fdbb3735	Add RISCV CSR registers	2021-11-07 20:36:04 +01:00
lazymio	172a2fbe6d	Support changing cpu model for riscv	2021-11-04 19:13:53 +01:00
lazymio	e62b0ef255	Add clang-format and format code to qemu code style	2021-10-29 12:44:49 +02:00
Nguyen Anh Quynh	aaaea14214	import Unicorn2	2021-10-03 22:14:44 +08:00