Commit Graph

61 Commits

Author SHA1 Message Date
mio
1dae6bb774 Correctly implement CR4 2025-02-18 10:43:52 +08:00
mio
791557e404 CI(full),CI(release): Should use if instead of ifdef 2025-02-11 17:44:24 +08:00
mio
b4eb933ec8 CI(full),CI(release): Do not refer to ATOMIC128 symbols if not available 2025-02-11 16:24:49 +08:00
0c512f91a1 Fix #1643
This adds an extra op to translator to allow the block hook sync pc in the very begining
2025-01-18 15:07:22 +08:00
EvianZhang
e97d084aec Add more EIP syncs for x86 target memory hooks (#2064)
Co-authored-by: lazymio <mio@lazym.io>
2025-01-04 15:59:20 +08:00
mio
fcca82bb28 Format code 2025-01-04 15:48:54 +08:00
Pedro Tôrres
7737e7b436 make i386 instructions RDTSC and RDTSCP hookable (#2066)
* instruction hooks for RDTSC and RDTSCP

Signed-off-by: Pedro Tôrres <t0rr3sp3dr0@gmail.com>

* update hookable instruction list

Signed-off-by: Pedro Tôrres <t0rr3sp3dr0@gmail.com>

* test RDTSC and RDTSCP instruction hooks

Signed-off-by: Pedro Tôrres <t0rr3sp3dr0@gmail.com>

---------

Signed-off-by: Pedro Tôrres <t0rr3sp3dr0@gmail.com>
Co-authored-by: mio <mio@lazym.io>
2024-12-20 17:17:23 +08:00
9ec1f604dc Fix regression: Setting eflags within the hook should take effect
This add an extra compute_eflags after the hooks
2024-12-07 15:56:56 +08:00
mio
c42cc0fe86 More 16-bits aligned cpu state targets 2024-10-17 16:33:59 +08:00
mio
ffeddd7579 use qemu_memalign for all cpu structs
Some structs, specically CPUARMState is 16-bytes aligned.

This causes segment fault because gcc tends to vectorize

the assignment of the struct with infamous movaps tricks.

Without this patch, we fail on manylinux with 2.17 glibc

in release mode in i686.

qemu_memalign will ensure the alignment across platforms.
2024-10-17 13:50:07 +08:00
0886e53572 Format code 2024-10-06 23:32:16 +08:00
mio
9f935f505e Revert previous break changes that return UC_ERR_ARG for non-existing registers
But print a warning instead
2024-10-02 16:03:58 +08:00
elicn
9af1df6543 Add read and write support for i386 ZMM0-31 2024-09-28 22:17:06 +03:00
elicn
5164dbd609 Add read and write support for i386 YMM8-31 2024-09-28 22:16:45 +03:00
elicn
e3675162ba Add read and write support for i386 XMM16-31 2024-09-28 22:15:00 +03:00
elicn
6cb9bfe5c0 Avoid updating CR3 when writing CR1 and CR2 2024-09-28 22:11:54 +03:00
elicn
433bb163d9 Add read and write cases for i386 CR8 2024-09-28 22:11:01 +03:00
Duncan Ogilvie
87610baa3f Fix emulator detection (#1966)
* Add a quick test helper macro to test_x86.c

* Add regression tests for bswap and rex prefixes

* Properly ignore REX prefixes when appropriate

* Fix bswap ax emulator detection
2024-07-19 11:11:21 +08:00
mio
24f898fb58 Fix #1869 2024-02-15 15:22:32 +08:00
a6fb2a6870 Save jit state before/after callback 2024-02-13 11:13:01 +08:00
Dimitris Glynos
9d8e639c69 fix fxsave fpip value, provide tests 2023-10-26 08:42:58 +03:00
c889258d8e Avoid overwriting tmp0 2023-08-06 21:25:37 +08:00
basavesh
cf5e75953d Backport qemu/qemu@75b208c
target/i386: fix operand order for PDEP and PEXT

For PDEP and PEXT, the mask is provided in the memory (mod+r/m)
operand, and therefore is loaded in s->T0 by gen_ldst_modrm.
The source is provided in the second source operand (VEX.vvvv)
and therefore is loaded in s->T1. Fix the order in which
they are passed to the helpers.
2023-08-03 13:12:39 +02:00
mio
a7a5d187e7 Backport 10b8eb94c0
target/i386: Verify memory operand for lcall and ljmp

These two opcodes only allow a memory operand.

Lacking the check for a register operand, we used the A0 temp

without initialization, which led to a tcg abort.
2023-06-30 20:21:56 +08:00
Robert Xiao
30d202b89e Simplify reg_read/reg_write, obtaining a perf boost.
Single reg_read/reg_write is now about 25% faster.
2023-06-16 15:23:42 -07:00
Robert Xiao
074566cf69 Slight refactoring to reduce code duplication.
This also comes with a performance bump due to inlining of reg_read/reg_write
(as they're only called once now) and the unlikely() on CHECK_REG_TYPE.
2023-06-16 15:23:42 -07:00
Robert Xiao
4055a5ab10 Implement uc_reg_{read,write}{,_batch}2 APIs.
These APIs take size parameters, which can be used to properly bounds-check the
inputs and outputs for various registers. Additionally, all backends now throw
UC_ERR_ARG if the input register numbers are invalid.

Completes #1831.
2023-06-16 15:23:42 -07:00
Robert Xiao
d7a806c026 Reformat code with format.sh 2023-06-16 15:23:41 -07:00
Takacs, Philipp
e96ac42b2e Remove MMU hacks
Unicorn has included some ugly hacks to provide a envirement where vaddr == paddr.
These hacks where to use the full 64 bit mappings on x86 without init the mmu
and some memory redirect for MIPS.

The UC_TLB_CPU mode defaults to vaddr == paddr, therfor these hacks aren't
required anymore.
2023-03-28 14:02:17 +02:00
Takacs, Philipp
e25419bb2d add virtuall tlb
this virtuall tlb allows to use mmu indipendent of the architectur
2023-03-28 13:50:11 +02:00
Takacs, Philipp
901034577a i386 call internal helper on special porpese register write
Some registers writes have side effects. i.e. write to cr3 flush the tlb,
if the PG bit is set.
2023-03-28 13:50:11 +02:00
Takacs, Philipp
f2eb1f4711 i386 mmu hack: Allow emulate usermode without mmu
This basicaly mappes virtual addresses to physical addresses 1:1 when
the mmu is disabled in the cpu. So you can use the full 64 bit addressspace
without required to configure the mmu.
2023-03-28 13:50:11 +02:00
Takacs, Philipp
b7b1a4d6b4 difference between stop_request and quit_request
quit_request is for internal use. This means the IP register was updated and
qemu needs to rebuild the translation blocks.

stop_request is set by the user (uc_emu_stop) to indecate that unicorn sould
stop emulating.
2023-03-07 14:38:49 +01:00
Takacs, Philipp
14404ef04b [x86] don't hardcode cpuid results
The cpuid results are set by the selected cpu.

CLOSES #1787
2023-02-27 12:34:38 +01:00
mio
133504b504 Fix wrong IP in x86_16 because of cs_base not substracted 2023-02-20 20:21:56 +01:00
mio
9c5358c759 Respect QEMU ZMM_Q to work on big endian hosts 2022-10-28 17:37:02 +02:00
Duncan Ogilvie
22ea31cdf7 Fail when VEX.L is set in SSE instructions (AVX is not supported)
Closes #1656
2022-07-20 13:48:31 +02:00
b827ebf4c3 Format code 2022-05-07 00:30:18 +02:00
345b63ee96 Only exit TB if pc is within the memory range 2022-05-07 00:16:31 +02:00
d946114dfe Set EFLAGS correctly on startup 2022-02-25 22:44:42 +01:00
d854e22301 Add x87 FPU registers #1524 2022-01-04 21:12:12 +01:00
mio
085ee07c73 No more hard-coded cpu models 2021-12-30 01:05:10 +01:00
ef6f8a2427 Fix x86 CPUID 2021-12-22 23:39:41 +01:00
7bb756249a Better design of cpuid instruction hook 2021-12-22 20:36:56 +01:00
87a391d549 Inline uc_tracecode when there is only exactly one hook 2021-11-21 16:44:39 +01:00
640251e1aa Leave out size parameter in callback 2021-11-09 00:21:34 +01:00
435ac71f47 Support changing cpu model for x86 2021-11-04 19:10:29 +01:00
6b5529fcb7 Merge pull request #1458 from bet4it/patch
Port some patches from Unicorn1 to Unicorn2
2021-11-03 20:59:42 +01:00
9818840f4e Add tests for UC_HOOK_TCG_OPCODE 2021-11-03 20:56:45 +01:00
bcf85be86d Add a new hook type UC_HOOK_TCG_OPCODE 2021-11-03 01:46:24 +01:00