Commit Graph

14 Commits

Author SHA1 Message Date
5a79d7879c Generate bindings 2022-04-16 17:50:32 +02:00
Ilya Leoshkevich
28c4c665f0 Add "holes" to where the removed x86 registers used to be
A number of x86 registers were removed for #1440, causing a change in
numbering for many other registers. This is causing inconveniences at
the moment, e.g. it's not possible to use the Unicorn2 shared library
as a drop-in replacement for the Unicorn1 one.

Restore the old numbering.

Fixes #1492.
2022-03-22 11:31:58 +01:00
c4b4189857 Update bindings 2022-01-04 21:12:52 +01:00
b9c0066a47 Format and naming 2021-11-04 20:04:57 +01:00
090686f8ed uc_ctl proposal (#1473)
* Add uc_ctl

* Add comments

* Slightly changed for bindings generation

* Generate bindings
2021-10-30 10:45:32 +08:00
Nguyen Anh Quynh
e8bd7ca087 bindings: update X86 register constants 2021-10-04 19:41:41 +08:00
Nguyen Anh Quynh
0a7223996d bindings: update constants from ARM registers 2021-10-04 01:04:43 +08:00
Dominik Maier
625399774c X64 base regs (#1166)
* x86: setup FS & GS base

* Fixed base register writes for x64, removed then for x16/x32 (the don't exist there?)

* FS reg comes before GS so the base regs do so, too

* added shebang to const_generator.py

* Added base regs to and added 'all' support to const_generator

Co-authored-by: naq <aquynh@gmail.com>
2020-05-05 08:34:51 +08:00
Nguyen Anh Quynh
738d102989 bindings: add newly added register MXCSR 2019-02-15 13:01:27 +08:00
Nguyen Anh Quynh
f4325f8c4e bindings: update to support X86 MSR id 2017-02-24 21:51:01 +08:00
Nguyen Anh Quynh
28b94d10b8 bindings: add X86 FPTAGS & FPCW registers after recent change in the core 2016-03-14 09:14:48 +08:00
Nguyen Anh Quynh
6986fa3947 x86: add new register enums for IDT, LDT, GDT & TR 2016-02-06 17:35:45 +08:00
enkomio
2c54f1a969 Solution refactoring and bug fixing 2016-01-04 16:59:05 +01:00
enkomio
5d3aac30e6 refactored code and minor bug fixing 2016-01-04 11:30:11 +01:00