Unlike some other architectures, RISC-V does not expose the current
privilege mode in any architecturally-defined register. That is intentional
to make it easier to implement virtualization in software, but a Unicorn
caller operates outside of the emulated hart and so it can and should be
able to observe and change the current privilege mode in order to properly
emulate certain behaviors of a real CPU.
The current privilege level is therefore now exposed as a new
pseudo-register using the name "priv", which matches the name of the
virtual register used by RISC-V's debug extension to allow the debugger
to read and change the privilege mode while the hart is halted. Unicorn's
use of it is conceptually similar to a debugger.
The bit encoding of this register is the same as specified in RISC-V Debug
Specification v1.0-rc3 Section 4.10.1. It's defined as a "virtual"
register exposing a subset of fields from the dcsr register, although here
it's implemented directly inside the Unicorn code because QEMU doesn't
currently have explicit support for the CSRs from the debug specification.
If it supports "dcsr" in a future release then this implementation could
change to wrap reading and writing that CSR and then projecting the "prv"
and "v" bitfields into the correct locations for the virtual register.
While the bindings conditionally compile code based on the cfg
flags, we still include the architecture support in emitted rust
code. This patch removes the ability to refer to architectures
that cannot possibly be supported.
The C function uc_mmio_map() allows to add seperate callback functions
and userdata for read and write. When the callback functions are NULL
unicorn don't try to call this functions.
Previous this patch, when i.e. read_callback was None the callback was set
to mmio_read_callback_proxy and the userdata was set to NULL. On a callback
the mmio_read_callback_proxy then tried to dereference the userdata and
caused a segfault.
fixes#1762
