5 Commits

Author	SHA1	Message	Date
lazymio	09aa0f944f	Merge QDucasse:riscv_extension_d ... Fix and close #1469 Fix test for riscv float points Fix the riscv cpu config we left out	2021-11-03 13:20:46 +01:00
lazymio	e62b0ef255	Add clang-format and format code to qemu code style	2021-10-29 12:44:49 +02:00
Quentin DUCASSE	5fd90ca1ef	Added 3 steps unit test	2021-10-19 17:20:10 +02:00
Quentin DUCASSE	47f986fc93	Unit test POC for RISCV issue	2021-10-19 17:12:52 +02:00
Nguyen Anh Quynh	aaaea14214	import Unicorn2	2021-10-03 22:14:44 +08:00