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Minor Python regress fixes (#2030)

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* Fix erronous method name

* Uncomment known failures

* Opportunistic improvements
This commit is contained in:
Eli
2024-10-13 11:35:42 +03:00
committed by GitHub
parent 7e32864774
commit fea3411803
6 changed files with 32 additions and 26 deletions
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16
tests/regress/core_ctl.py
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@@ -53,8 +53,8 @@ class TestCtl(regress.RegressTest):
# set page size to 2 MiB; this should work
uc.ctl_set_page_size(SIZE_2MB)
# BUG! was it set properly?
# self.assertEqual(SIZE_2MB, uc.ctl_get_page_size())
# was it set properly?
self.assertEqual(SIZE_2MB, uc.ctl_get_page_size())
# set a page size which is not a power of 2
with self.assertRaises(UcError) as ex:
@@ -62,8 +62,8 @@ class TestCtl(regress.RegressTest):
self.assertEqual(UC_ERR_ARG, ex.exception.errno)
# BUG! are we still with the valid value?
# self.assertEqual(SIZE_2MB, uc.ctl_get_page_size())
# are we still with the valid value?
self.assertEqual(SIZE_2MB, uc.ctl_get_page_size())
# force uc to complete its initialization by triggering a random api
uc.ctl_flush_tb()
@@ -74,8 +74,8 @@ class TestCtl(regress.RegressTest):
self.assertEqual(UC_ERR_ARG, ex.exception.errno)
# BUG! are we still with the valid value?
# self.assertEqual(SIZE_2MB, uc.ctl_get_page_size())
# are we still with the valid value?
self.assertEqual(SIZE_2MB, uc.ctl_get_page_size())
def test_timeout(self):
MILLIS_1S = 1000
@@ -156,7 +156,7 @@ class TestCtl(regress.RegressTest):
uc.mem_write(MAPPING_HI, NOPSLED)
# this should prevents us from mapping to high addresses
uc.ctl_tlb_mode(UC_TLB_CPU)
uc.ctl_set_tlb_mode(UC_TLB_CPU)
# this should fail
with self.assertRaises(UcError) as ex:
@@ -167,7 +167,7 @@ class TestCtl(regress.RegressTest):
# ------------------------------------------------------
# this should allow us mapping to high addresses
uc.ctl_tlb_mode(UC_TLB_VIRTUAL)
uc.ctl_set_tlb_mode(UC_TLB_VIRTUAL)
# this should ok now
uc.emu_start(MAPPING_HI, MAPPING_HI + len(NOPSLED))