diff --git a/tests/regress/arm64_reg_rw_w0_w30.py b/tests/regress/arm64_reg_rw_w0_w30.py index fc34ea4c..42b2f149 100644 --- a/tests/regress/arm64_reg_rw_w0_w30.py +++ b/tests/regress/arm64_reg_rw_w0_w30.py @@ -1,10 +1,10 @@ #!/usr/bin/python +import regress + from unicorn import * from unicorn.arm64_const import * -from unicorn.x86_const import * -import regress class Arm64RegReadWriteW0ThroughW30(regress.RegressTest): """ @@ -14,17 +14,26 @@ class Arm64RegReadWriteW0ThroughW30(regress.RegressTest): def runTest(self): uc = Uc(UC_ARCH_ARM64, UC_MODE_ARM) - - uc.reg_write(UC_ARM64_REG_X0, 0x1234567890abcdef) - self.assertEquals(uc.reg_read(UC_ARM64_REG_X0), 0x1234567890abcdef) - self.assertEquals(uc.reg_read(UC_ARM64_REG_W0), 0x90abcdef) - - uc.reg_write(UC_ARM64_REG_X30, 0xa1b2c3d4e5f6a7b8) - self.assertEquals(uc.reg_read(UC_ARM64_REG_W30), 0xe5f6a7b8) - uc.reg_write(UC_ARM64_REG_W30, 0xaabbccdd) - self.assertEquals(uc.reg_read(UC_ARM64_REG_X30), 0xa1b2c3d4aabbccdd) - self.assertEquals(uc.reg_read(UC_ARM64_REG_W30), 0xaabbccdd) + expected = 0x1234567890abcdef + + uc.reg_write(UC_ARM64_REG_X0, expected) + self.assertEqual(uc.reg_read(UC_ARM64_REG_X0), expected) + self.assertEqual(uc.reg_read(UC_ARM64_REG_W0), expected & 0xffffffff) + + # ---------------------------------------------------------- + + expected = 0xa1b2c3d4e5f6a7b8 + + uc.reg_write(UC_ARM64_REG_X30, expected) + self.assertEqual(uc.reg_read(UC_ARM64_REG_W30), expected & 0xffffffff) + + expected_lo = 0xaabbccdd + + uc.reg_write(UC_ARM64_REG_W30, expected_lo) + self.assertEqual(uc.reg_read(UC_ARM64_REG_X30), (expected & ~0xffffffff) | expected_lo) + self.assertEqual(uc.reg_read(UC_ARM64_REG_W30), expected_lo) + if __name__ == '__main__': regress.main() diff --git a/tests/regress/core_ctl.py b/tests/regress/core_ctl.py index 9cf1e1c2..730c1e8a 100644 --- a/tests/regress/core_ctl.py +++ b/tests/regress/core_ctl.py @@ -53,8 +53,8 @@ class TestCtl(regress.RegressTest): # set page size to 2 MiB; this should work uc.ctl_set_page_size(SIZE_2MB) - # BUG! was it set properly? - # self.assertEqual(SIZE_2MB, uc.ctl_get_page_size()) + # was it set properly? + self.assertEqual(SIZE_2MB, uc.ctl_get_page_size()) # set a page size which is not a power of 2 with self.assertRaises(UcError) as ex: @@ -62,8 +62,8 @@ class TestCtl(regress.RegressTest): self.assertEqual(UC_ERR_ARG, ex.exception.errno) - # BUG! are we still with the valid value? - # self.assertEqual(SIZE_2MB, uc.ctl_get_page_size()) + # are we still with the valid value? + self.assertEqual(SIZE_2MB, uc.ctl_get_page_size()) # force uc to complete its initialization by triggering a random api uc.ctl_flush_tb() @@ -74,8 +74,8 @@ class TestCtl(regress.RegressTest): self.assertEqual(UC_ERR_ARG, ex.exception.errno) - # BUG! are we still with the valid value? - # self.assertEqual(SIZE_2MB, uc.ctl_get_page_size()) + # are we still with the valid value? + self.assertEqual(SIZE_2MB, uc.ctl_get_page_size()) def test_timeout(self): MILLIS_1S = 1000 @@ -156,7 +156,7 @@ class TestCtl(regress.RegressTest): uc.mem_write(MAPPING_HI, NOPSLED) # this should prevents us from mapping to high addresses - uc.ctl_tlb_mode(UC_TLB_CPU) + uc.ctl_set_tlb_mode(UC_TLB_CPU) # this should fail with self.assertRaises(UcError) as ex: @@ -167,7 +167,7 @@ class TestCtl(regress.RegressTest): # ------------------------------------------------------ # this should allow us mapping to high addresses - uc.ctl_tlb_mode(UC_TLB_VIRTUAL) + uc.ctl_set_tlb_mode(UC_TLB_VIRTUAL) # this should ok now uc.emu_start(MAPPING_HI, MAPPING_HI + len(NOPSLED)) diff --git a/tests/regress/high_mem.py b/tests/regress/high_mem.py index 7c46c71d..07a94200 100644 --- a/tests/regress/high_mem.py +++ b/tests/regress/high_mem.py @@ -30,7 +30,7 @@ class TestMem(regress.RegressTest): base = 0x0010000000000000 - self.uc.ctl_tlb_mode(UC_TLB_VIRTUAL) + self.uc.ctl_set_tlb_mode(UC_TLB_VIRTUAL) for i in range(12): code = base << i @@ -49,7 +49,7 @@ class TestMem(regress.RegressTest): base = 0x0010000000000000 - self.uc.ctl_tlb_mode(UC_TLB_CPU) + self.uc.ctl_set_tlb_mode(UC_TLB_CPU) for i in range(12): code = base << i diff --git a/tests/regress/hook_readonly_write_local.py b/tests/regress/hook_readonly_write_local.py index 60e6de45..af1ed90d 100755 --- a/tests/regress/hook_readonly_write_local.py +++ b/tests/regress/hook_readonly_write_local.py @@ -23,7 +23,6 @@ def hook_mem_read(uc, access, address, size, value, data): class REP(regress.RegressTest): - @regress.unittest.skip('writing to a UC_PROT_READ area will segfault Unicorn') def runTest(self): mu = Uc(UC_ARCH_X86, UC_MODE_32) diff --git a/tests/regress/memmap_segfault.py b/tests/regress/memmap_segfault.py index 5d217e62..c2e84933 100755 --- a/tests/regress/memmap_segfault.py +++ b/tests/regress/memmap_segfault.py @@ -31,8 +31,6 @@ class MmapSeg2(regress.RegressTest): uc.mem_map(0x2000, 0x4000) uc.mem_write(0x1000, b' ' * 0x1004) - self.assertTrue(True, 'If not reached, then we have BUG (crash on x86_64 Linux).') - if __name__ == '__main__': regress.main() diff --git a/tests/regress/sparc_reg.py b/tests/regress/sparc_reg.py index abf43133..12a28e09 100755 --- a/tests/regress/sparc_reg.py +++ b/tests/regress/sparc_reg.py @@ -100,7 +100,7 @@ class TestSparcRegRead(regress.RegressTest): self.assertEqual(1, uc.reg_read(UC_SPARC_REG_I7)) # BUG: PC seems to get reset to 4 when done executing - # self.assertEqual(4 * 32, uc.reg_read(UC_SPARC_REG_PC)) # make sure we executed all instructions + self.assertEqual(4 * 32, uc.reg_read(UC_SPARC_REG_PC)) # make sure we executed all instructions self.assertEqual(101, uc.reg_read(UC_SPARC_REG_SP)) self.assertEqual(201, uc.reg_read(UC_SPARC_REG_FP))