Merge branch 'dev' into patch

.clang-format

@@ -0,0 +1,16 @@
+BasedOnStyle: LLVM
+IndentWidth: 4
+UseTab: Never
+BreakBeforeBraces: Linux
+AllowShortIfStatementsOnASingleLine: Never
+AllowShortCaseLabelsOnASingleLine: false
+AllowShortBlocksOnASingleLine: Empty
+AllowShortFunctionsOnASingleLine: Empty
+AllowShortLoopsOnASingleLine: false
+IndentCaseLabels: false
+ColumnLimit: 80
+SortIncludes: false
+AllowShortLambdasOnASingleLine: Inline
+AlwaysBreakBeforeMultilineStrings: false
+BreakStringLiterals: true
+PointerAlignment: Right

.github/workflows/Crate-publishing.yml

@@ -15,7 +15,7 @@ on:
   pull_request:
 
 env:
-  CI: true
+  UNICORN_VERSION: dev
 
 jobs:
   build:

CMakeLists.txt

@@ -1108,6 +1108,11 @@ if (UNICORN_HAS_RISCV)
     set(UNICORN_TEST_FILE ${UNICORN_TEST_FILE} test_riscv)
 endif()
 
+# Extra tests
+set(UNICORN_TEST_FILE ${UNICORN_TEST_FILE} test_mem)
+set(UNICORN_TEST_FILE ${UNICORN_TEST_FILE} test_ctl)
+set(UNICORN_SAMPLE_FILE ${UNICORN_SAMPLE_FILE} sample_ctl)
+
 target_compile_options(unicorn PRIVATE
     ${UNICORN_COMPILE_OPTIONS}
 )

bindings/Makefile

@@ -24,8 +24,8 @@ build:
 	$(MAKE) -C go gen_const
 	$(MAKE) -C java gen_const
 	$(MAKE) -C ruby gen_const
-	python const_generator.py dotnet
-	python const_generator.py pascal
+	python3 const_generator.py dotnet
+	python3 const_generator.py pascal
 
 install: build
 	$(MAKE) -C python install
@@ -40,7 +40,7 @@ python:
 %.c.txt: c
 	$(ENV_VARS) ../samples/$(@:%.c.txt=%) > $@
 %.py.txt: python
-	$(ENV_VARS) python python/$(@:%.txt=%) > $@
+	$(ENV_VARS) python3 python/$(@:%.txt=%) > $@
 
 %.py.test: %.c.txt %.py.txt
 	$(DIFF) -u $(@:%.py.test=%.c.txt) $(@:%.py.test=%.py.txt)

bindings/const_generator.py

@@ -136,7 +136,20 @@ def gen(lang):
 
         previous = {}
         count = 0
-        for line in lines:
+        skip = 0
+        in_comment = False
+        
+        for lno, line in enumerate(lines):
+            if "/*" in line:
+                in_comment = True
+            if "*/" in line:
+                in_comment = False
+            if in_comment:
+                continue
+            if skip > 0:
+                # Due to clang-format, values may come up in the next line
+                skip -= 1
+                continue
             line = line.strip()
 
             if line.startswith(MARKUP):  # markup for comments
@@ -148,6 +161,8 @@ def gen(lang):
                 continue
 
             tmp = line.strip().split(',')
+            if len(tmp) >= 2 and tmp[0] != "#define" and not tmp[0].startswith("UC_"):
+                continue
             for t in tmp:
                 t = t.strip()
                 if not t or t.startswith('//'): continue
@@ -159,18 +174,52 @@ def gen(lang):
                     define = True
                     f.pop(0)
                     f.insert(1, '=')
-
-                if f[0].startswith("UC_" + prefix.upper()):
+                if f[0].startswith("UC_" + prefix.upper()) or f[0].startswith("UC_CPU"):
                     if len(f) > 1 and f[1] not in ('//', '='):
                         print("WARNING: Unable to convert %s" % f)
                         print("  Line =", line)
                         continue
                     elif len(f) > 1 and f[1] == '=':
-                        rhs = ''.join(f[2:])
+                        # Like:
+                        # UC_A = 
+                        #       (1 << 2)
+                        # #define UC_B \
+                        #              (UC_A | UC_C)
+                        # Let's search the next line
+                        if len(f) == 2:
+                            if lno == len(lines) - 1:
+                                print("WARNING: Unable to convert %s" % f)
+                                print("  Line =", line)
+                                continue
+                            skip += 1
+                            next_line = lines[lno + 1]
+                            next_line_tmp = next_line.strip().split(",")
+                            rhs = next_line_tmp[0]
+                        elif f[-1] == "\\":
+                            idx = 0
+                            rhs = ""
+                            while True:
+                                idx += 1
+                                if lno + idx == len(lines):
+                                    print("WARNING: Unable to convert %s" % f)
+                                    print("  Line =", line)
+                                    continue
+                                skip += 1
+                                next_line = lines[lno + idx]
+                                next_line_f = re.split('\s+', next_line.strip())
+                                if next_line_f[-1] == "\\":
+                                    rhs += "".join(next_line_f[:-1])
+                                else:
+                                    rhs += next_line.strip()
+                                    break
+                        else:
+                            rhs = ''.join(f[2:])
                     else:
                         rhs = str(count)
 
+                    
                     lhs = f[0].strip()
+                    #print(f'lhs: {lhs} rhs: {rhs} f:{f}')
                     # evaluate bitshifts in constants e.g. "UC_X86 = 1 << 1"
                     match = re.match(r'(?P<rhs>\s*\d+\s*<<\s*\d+\s*)', rhs)
                     if match:

bindings/dotnet/UnicornManaged/Const/Arm.fs

@@ -7,6 +7,40 @@ open System
 [<AutoOpen>]
 module Arm =
 
+    let UC_CPU_ARM_926 = 0
+    let UC_CPU_ARM_946 = 1
+    let UC_CPU_ARM_1026 = 2
+    let UC_CPU_ARM_1136_R2 = 3
+    let UC_CPU_ARM_1136 = 4
+    let UC_CPU_ARM_1176 = 5
+    let UC_CPU_ARM_11MPCORE = 6
+    let UC_CPU_ARM_CORTEX_M0 = 7
+    let UC_CPU_ARM_CORTEX_M3 = 8
+    let UC_CPU_ARM_CORTEX_M4 = 9
+    let UC_CPU_ARM_CORTEX_M7 = 10
+    let UC_CPU_ARM_CORTEX_M33 = 11
+    let UC_CPU_ARM_CORTEX_R5 = 12
+    let UC_CPU_ARM_CORTEX_R5F = 13
+    let UC_CPU_ARM_CORTEX_A8 = 14
+    let UC_CPU_ARM_CORTEX_A9 = 15
+    let UC_CPU_ARM_CORTEX_A7 = 16
+    let UC_CPU_ARM_CORTEX_A15 = 17
+    let UC_CPU_ARM_TI925T = 18
+    let UC_CPU_ARM_SA1100 = 19
+    let UC_CPU_ARM_SA1110 = 20
+    let UC_CPU_ARM_PXA250 = 21
+    let UC_CPU_ARM_PXA255 = 22
+    let UC_CPU_ARM_PXA260 = 23
+    let UC_CPU_ARM_PXA261 = 24
+    let UC_CPU_ARM_PXA262 = 25
+    let UC_CPU_ARM_PXA270A0 = 26
+    let UC_CPU_ARM_PXA270A1 = 27
+    let UC_CPU_ARM_PXA270B0 = 28
+    let UC_CPU_ARM_PXA270B1 = 29
+    let UC_CPU_ARM_PXA270C0 = 30
+    let UC_CPU_ARM_PXA270C5 = 31
+    let UC_CPU_ARM_MAX = 32
+
     // ARM registers
 
     let UC_ARM_REG_INVALID = 0

bindings/dotnet/UnicornManaged/Const/Arm64.fs

@@ -7,6 +7,11 @@ open System
 [<AutoOpen>]
 module Arm64 =
 
+    let UC_CPU_AARCH64_A57 = 0
+    let UC_CPU_AARCH64_A53 = 1
+    let UC_CPU_AARCH64_A72 = 2
+    let UC_CPU_AARCH64_MAX = 3
+
     // ARM64 registers
 
     let UC_ARM64_REG_INVALID = 0

bindings/dotnet/UnicornManaged/Const/Common.fs

@@ -112,6 +112,22 @@ module Common =
     let UC_QUERY_ARCH = 3
     let UC_QUERY_TIMEOUT = 4
 
+    let UC_CTL_IO_NONE = 0
+    let UC_CTL_IO_WRITE = 1
+    let UC_CTL_IO_READ = 2
+    let UC_CTL_IO_READ_WRITE = 3
+
+    let UC_CTL_UC_MODE = 0
+    let UC_CTL_UC_PAGE_SIZE = 1
+    let UC_CTL_UC_ARCH = 2
+    let UC_CTL_UC_TIMEOUT = 3
+    let UC_CTL_UC_EXITS_CNT = 4
+    let UC_CTL_UC_EXITS = 5
+    let UC_CTL_CPU_MODEL = 6
+    let UC_CTL_TB_EDGE = 7
+    let UC_CTL_TB_REQUEST_CACHE = 8
+    let UC_CTL_TB_REMOVE_CACHE = 9
+
     let UC_PROT_NONE = 0
     let UC_PROT_READ = 1
     let UC_PROT_WRITE = 2

bindings/dotnet/UnicornManaged/Const/M68k.fs

@@ -7,6 +7,16 @@ open System
 [<AutoOpen>]
 module M68k =
 
+    let UC_CPU_M5206_CPU = 0
+    let UC_CPU_M68000_CPU = 1
+    let UC_CPU_M68020_CPU = 2
+    let UC_CPU_M68030_CPU = 3
+    let UC_CPU_M68040_CPU = 4
+    let UC_CPU_M68060_CPU = 5
+    let UC_CPU_M5208_CPU = 6
+    let UC_CPU_CFV4E_CPU = 7
+    let UC_CPU_ANY_CPU = 8
+
     // M68K registers
 
     let UC_M68K_REG_INVALID = 0

bindings/dotnet/UnicornManaged/Const/Mips.fs

@@ -7,6 +7,36 @@ open System
 [<AutoOpen>]
 module Mips =
 
+    let UC_CPU_MIPS_4KC = 0
+    let UC_CPU_MIPS_4KM = 1
+    let UC_CPU_MIPS_4KECR1 = 2
+    let UC_CPU_MIPS_4KEMR1 = 3
+    let UC_CPU_MIPS_4KEC = 4
+    let UC_CPU_MIPS_4KEM = 5
+    let UC_CPU_MIPS_24KC = 6
+    let UC_CPU_MIPS_24KEC = 7
+    let UC_CPU_MIPS_24KF = 8
+    let UC_CPU_MIPS_34KF = 9
+    let UC_CPU_MIPS_74KF = 10
+    let UC_CPU_MIPS_M14K = 11
+    let UC_CPU_MIPS_M14KC = 12
+    let UC_CPU_MIPS_P5600 = 13
+    let UC_CPU_MIPS_MIPS32R6_GENERIC = 14
+    let UC_CPU_MIPS_I7200 = 15
+    let UC_CPU_MIPS_R4000 = 16
+    let UC_CPU_MIPS_VR5432 = 17
+    let UC_CPU_MIPS_5KC = 18
+    let UC_CPU_MIPS_5KF = 19
+    let UC_CPU_MIPS_20KC = 20
+    let UC_CPU_MIPS_MIPS64R2_GENERIC = 21
+    let UC_CPU_MIPS_5KEC = 22
+    let UC_CPU_MIPS_5KEF = 23
+    let UC_CPU_MIPS_I6400 = 24
+    let UC_CPU_MIPS_I6500 = 25
+    let UC_CPU_MIPS_LOONGSON_2E = 26
+    let UC_CPU_MIPS_LOONGSON_2F = 27
+    let UC_CPU_MIPS_MIPS64DSPR2 = 28
+
     // MIPS registers
 
     let UC_MIPS_REG_INVALID = 0

bindings/dotnet/UnicornManaged/Const/Ppc.fs

@@ -7,6 +7,307 @@ open System
 [<AutoOpen>]
 module Ppc =
 
+    let UC_CPU_PPC_401A1 = 0
+    let UC_CPU_PPC_401B2 = 1
+    let UC_CPU_PPC_401C2 = 2
+    let UC_CPU_PPC_401D2 = 3
+    let UC_CPU_PPC_401E2 = 4
+    let UC_CPU_PPC_401F2 = 5
+    let UC_CPU_PPC_401G2 = 6
+    let UC_CPU_PPC_COBRA = 7
+    let UC_CPU_PPC_403GA = 8
+    let UC_CPU_PPC_403GB = 9
+    let UC_CPU_PPC_403GC = 10
+    let UC_CPU_PPC_403GCX = 11
+    let UC_CPU_PPC_405D2 = 12
+    let UC_CPU_PPC_405D4 = 13
+    let UC_CPU_PPC_405CRA = 14
+    let UC_CPU_PPC_405CRB = 15
+    let UC_CPU_PPC_405CRC = 16
+    let UC_CPU_PPC_405EP = 17
+    let UC_CPU_PPC_405EZ = 18
+    let UC_CPU_PPC_405GPA = 19
+    let UC_CPU_PPC_405GPB = 20
+    let UC_CPU_PPC_405GPC = 21
+    let UC_CPU_PPC_405GPD = 22
+    let UC_CPU_PPC_405GPR = 23
+    let UC_CPU_PPC_405LP = 24
+    let UC_CPU_PPC_NPE405H = 25
+    let UC_CPU_PPC_NPE405H2 = 26
+    let UC_CPU_PPC_NPE405L = 27
+    let UC_CPU_PPC_NPE4GS3 = 28
+    let UC_CPU_PPC_STB03 = 29
+    let UC_CPU_PPC_STB04 = 30
+    let UC_CPU_PPC_STB25 = 31
+    let UC_CPU_PPC_X2VP4 = 32
+    let UC_CPU_PPC_440_XILINX = 33
+    let UC_CPU_PPC_440EPA = 34
+    let UC_CPU_PPC_440EPB = 35
+    let UC_CPU_PPC_440GPB = 36
+    let UC_CPU_PPC_440GPC = 37
+    let UC_CPU_PPC_440GRX = 38
+    let UC_CPU_PPC_440GXA = 39
+    let UC_CPU_PPC_440GXB = 40
+    let UC_CPU_PPC_440GXC = 41
+    let UC_CPU_PPC_440GXF = 42
+    let UC_CPU_PPC_440SP = 43
+    let UC_CPU_PPC_440SP2 = 44
+    let UC_CPU_PPC_440SPE = 45
+    let UC_CPU_PPC_460EXB = 46
+    let UC_CPU_PPC_MPC5XX = 47
+    let UC_CPU_PPC_MPC8XX = 48
+    let UC_CPU_PPC_G2 = 49
+    let UC_CPU_PPC_G2H4 = 50
+    let UC_CPU_PPC_G2GP = 51
+    let UC_CPU_PPC_G2LS = 52
+    let UC_CPU_PPC_MPC603 = 53
+    let UC_CPU_PPC_G2_HIP3 = 54
+    let UC_CPU_PPC_G2_HIP4 = 55
+    let UC_CPU_PPC_G2LE = 56
+    let UC_CPU_PPC_G2LEGP = 57
+    let UC_CPU_PPC_G2LELS = 58
+    let UC_CPU_PPC_G2LEGP1 = 59
+    let UC_CPU_PPC_G2LEGP3 = 60
+    let UC_CPU_PPC_E200Z5 = 61
+    let UC_CPU_PPC_E200Z6 = 62
+    let UC_CPU_PPC_E300C1 = 63
+    let UC_CPU_PPC_E300C2 = 64
+    let UC_CPU_PPC_E300C3 = 65
+    let UC_CPU_PPC_E300C4 = 66
+    let UC_CPU_PPC_E500V1_V10 = 67
+    let UC_CPU_PPC_E500V1_V20 = 68
+    let UC_CPU_PPC_E500V2_V10 = 69
+    let UC_CPU_PPC_E500V2_V11 = 70
+    let UC_CPU_PPC_E500V2_V20 = 71
+    let UC_CPU_PPC_E500V2_V21 = 72
+    let UC_CPU_PPC_E500V2_V22 = 73
+    let UC_CPU_PPC_E500V2_V30 = 74
+    let UC_CPU_PPC_E500MC = 75
+    let UC_CPU_PPC_E5500 = 76
+    let UC_CPU_PPC_E6500 = 77
+    let UC_CPU_PPC_E600 = 78
+    let UC_CPU_PPC_601_V0 = 79
+    let UC_CPU_PPC_601_V1 = 80
+    let UC_CPU_PPC_601_V2 = 81
+    let UC_CPU_PPC_602 = 82
+    let UC_CPU_PPC_603 = 83
+    let UC_CPU_PPC_603E_V11 = 84
+    let UC_CPU_PPC_603E_V12 = 85
+    let UC_CPU_PPC_603E_V13 = 86
+    let UC_CPU_PPC_603E_V14 = 87
+    let UC_CPU_PPC_603E_V22 = 88
+    let UC_CPU_PPC_603E_V3 = 89
+    let UC_CPU_PPC_603E_V4 = 90
+    let UC_CPU_PPC_603E_V41 = 91
+    let UC_CPU_PPC_603E7T = 92
+    let UC_CPU_PPC_603E7V = 93
+    let UC_CPU_PPC_603E7V1 = 94
+    let UC_CPU_PPC_603E7V2 = 95
+    let UC_CPU_PPC_603E7 = 96
+    let UC_CPU_PPC_603P = 97
+    let UC_CPU_PPC_604 = 98
+    let UC_CPU_PPC_604E_V10 = 99
+    let UC_CPU_PPC_604E_V22 = 100
+    let UC_CPU_PPC_604E_V24 = 101
+    let UC_CPU_PPC_604R = 102
+    let UC_CPU_PPC_7X0_V10 = 103
+    let UC_CPU_PPC_7X0_V20 = 104
+    let UC_CPU_PPC_7X0_V21 = 105
+    let UC_CPU_PPC_7X0_V22 = 106
+    let UC_CPU_PPC_7X0_V30 = 107
+    let UC_CPU_PPC_7X0_V31 = 108
+    let UC_CPU_PPC_740E = 109
+    let UC_CPU_PPC_750E = 110
+    let UC_CPU_PPC_7X0P = 111
+    let UC_CPU_PPC_750CL_V10 = 112
+    let UC_CPU_PPC_750CL_V20 = 113
+    let UC_CPU_PPC_750CX_V10 = 114
+    let UC_CPU_PPC_750CX_V20 = 115
+    let UC_CPU_PPC_750CX_V21 = 116
+    let UC_CPU_PPC_750CX_V22 = 117
+    let UC_CPU_PPC_750CXE_V21 = 118
+    let UC_CPU_PPC_750CXE_V22 = 119
+    let UC_CPU_PPC_750CXE_V23 = 120
+    let UC_CPU_PPC_750CXE_V24 = 121
+    let UC_CPU_PPC_750CXE_V24B = 122
+    let UC_CPU_PPC_750CXE_V30 = 123
+    let UC_CPU_PPC_750CXE_V31 = 124
+    let UC_CPU_PPC_750CXE_V31B = 125
+    let UC_CPU_PPC_750CXR = 126
+    let UC_CPU_PPC_750FL = 127
+    let UC_CPU_PPC_750FX_V10 = 128
+    let UC_CPU_PPC_750FX_V20 = 129
+    let UC_CPU_PPC_750FX_V21 = 130
+    let UC_CPU_PPC_750FX_V22 = 131
+    let UC_CPU_PPC_750FX_V23 = 132
+    let UC_CPU_PPC_750GL = 133
+    let UC_CPU_PPC_750GX_V10 = 134
+    let UC_CPU_PPC_750GX_V11 = 135
+    let UC_CPU_PPC_750GX_V12 = 136
+    let UC_CPU_PPC_750L_V20 = 137
+    let UC_CPU_PPC_750L_V21 = 138
+    let UC_CPU_PPC_750L_V22 = 139
+    let UC_CPU_PPC_750L_V30 = 140
+    let UC_CPU_PPC_750L_V32 = 141
+    let UC_CPU_PPC_7X5_V10 = 142
+    let UC_CPU_PPC_7X5_V11 = 143
+    let UC_CPU_PPC_7X5_V20 = 144
+    let UC_CPU_PPC_7X5_V21 = 145
+    let UC_CPU_PPC_7X5_V22 = 146
+    let UC_CPU_PPC_7X5_V23 = 147
+    let UC_CPU_PPC_7X5_V24 = 148
+    let UC_CPU_PPC_7X5_V25 = 149
+    let UC_CPU_PPC_7X5_V26 = 150
+    let UC_CPU_PPC_7X5_V27 = 151
+    let UC_CPU_PPC_7X5_V28 = 152
+    let UC_CPU_PPC_7400_V10 = 153
+    let UC_CPU_PPC_7400_V11 = 154
+    let UC_CPU_PPC_7400_V20 = 155
+    let UC_CPU_PPC_7400_V21 = 156
+    let UC_CPU_PPC_7400_V22 = 157
+    let UC_CPU_PPC_7400_V26 = 158
+    let UC_CPU_PPC_7400_V27 = 159
+    let UC_CPU_PPC_7400_V28 = 160
+    let UC_CPU_PPC_7400_V29 = 161
+    let UC_CPU_PPC_7410_V10 = 162
+    let UC_CPU_PPC_7410_V11 = 163
+    let UC_CPU_PPC_7410_V12 = 164
+    let UC_CPU_PPC_7410_V13 = 165
+    let UC_CPU_PPC_7410_V14 = 166
+    let UC_CPU_PPC_7448_V10 = 167
+    let UC_CPU_PPC_7448_V11 = 168
+    let UC_CPU_PPC_7448_V20 = 169
+    let UC_CPU_PPC_7448_V21 = 170
+    let UC_CPU_PPC_7450_V10 = 171
+    let UC_CPU_PPC_7450_V11 = 172
+    let UC_CPU_PPC_7450_V12 = 173
+    let UC_CPU_PPC_7450_V20 = 174
+    let UC_CPU_PPC_7450_V21 = 175
+    let UC_CPU_PPC_74X1_V23 = 176
+    let UC_CPU_PPC_74X1_V210 = 177
+    let UC_CPU_PPC_74X5_V10 = 178
+    let UC_CPU_PPC_74X5_V21 = 179
+    let UC_CPU_PPC_74X5_V32 = 180
+    let UC_CPU_PPC_74X5_V33 = 181
+    let UC_CPU_PPC_74X5_V34 = 182
+    let UC_CPU_PPC_74X7_V10 = 183
+    let UC_CPU_PPC_74X7_V11 = 184
+    let UC_CPU_PPC_74X7_V12 = 185
+    let UC_CPU_PPC_74X7A_V10 = 186
+    let UC_CPU_PPC_74X7A_V11 = 187
+    let UC_CPU_PPC_74X7A_V12 = 188
+    let UC_CPU_PPC_IOP480 = 1
+    let UC_CPU_PPC_X2VP20 = 42
+    let UC_CPU_PPC_440GRA = 35
+    let UC_CPU_PPC_440EPX = 38
+    let UC_CPU_PPC_MPC5200_V10 = 59
+    let UC_CPU_PPC_MPC5200_V11 = 59
+    let UC_CPU_PPC_MPC5200_V12 = 59
+    let UC_CPU_PPC_MPC5200B_V20 = 59
+    let UC_CPU_PPC_MPC5200B_V21 = 59
+    let UC_CPU_PPC_MPC834X = 63
+    let UC_CPU_PPC_MPC837X = 66
+    let UC_CPU_PPC_E500 = 73
+    let UC_CPU_PPC_MPC8533_V10 = 72
+    let UC_CPU_PPC_MPC8533_V11 = 73
+    let UC_CPU_PPC_MPC8533E_V10 = 72
+    let UC_CPU_PPC_MPC8533E_V11 = 73
+    let UC_CPU_PPC_MPC8540_V10 = 67
+    let UC_CPU_PPC_MPC8540_V20 = 68
+    let UC_CPU_PPC_MPC8540_V21 = 68
+    let UC_CPU_PPC_MPC8541_V10 = 68
+    let UC_CPU_PPC_MPC8541_V11 = 68
+    let UC_CPU_PPC_MPC8541E_V10 = 68
+    let UC_CPU_PPC_MPC8541E_V11 = 68
+    let UC_CPU_PPC_MPC8543_V10 = 69
+    let UC_CPU_PPC_MPC8543_V11 = 70
+    let UC_CPU_PPC_MPC8543_V20 = 71
+    let UC_CPU_PPC_MPC8543_V21 = 72
+    let UC_CPU_PPC_MPC8543E_V10 = 69
+    let UC_CPU_PPC_MPC8543E_V11 = 70
+    let UC_CPU_PPC_MPC8543E_V20 = 71
+    let UC_CPU_PPC_MPC8543E_V21 = 72
+    let UC_CPU_PPC_MPC8544_V10 = 72
+    let UC_CPU_PPC_MPC8544_V11 = 73
+    let UC_CPU_PPC_MPC8544E_V11 = 73
+    let UC_CPU_PPC_MPC8544E_V10 = 72
+    let UC_CPU_PPC_MPC8545_V10 = 69
+    let UC_CPU_PPC_MPC8545_V20 = 71
+    let UC_CPU_PPC_MPC8545_V21 = 72
+    let UC_CPU_PPC_MPC8545E_V10 = 69
+    let UC_CPU_PPC_MPC8545E_V20 = 71
+    let UC_CPU_PPC_MPC8545E_V21 = 72
+    let UC_CPU_PPC_MPC8547E_V10 = 69
+    let UC_CPU_PPC_MPC8547E_V20 = 71
+    let UC_CPU_PPC_MPC8547E_V21 = 72
+    let UC_CPU_PPC_MPC8548_V10 = 69
+    let UC_CPU_PPC_MPC8548_V11 = 70
+    let UC_CPU_PPC_MPC8548_V20 = 71
+    let UC_CPU_PPC_MPC8548_V21 = 72
+    let UC_CPU_PPC_MPC8548E_V10 = 69
+    let UC_CPU_PPC_MPC8548E_V11 = 70
+    let UC_CPU_PPC_MPC8548E_V20 = 71
+    let UC_CPU_PPC_MPC8548E_V21 = 72
+    let UC_CPU_PPC_MPC8555_V10 = 69
+    let UC_CPU_PPC_MPC8555_V11 = 70
+    let UC_CPU_PPC_MPC8555E_V10 = 69
+    let UC_CPU_PPC_MPC8555E_V11 = 70
+    let UC_CPU_PPC_MPC8560_V10 = 69
+    let UC_CPU_PPC_MPC8560_V20 = 71
+    let UC_CPU_PPC_MPC8560_V21 = 72
+    let UC_CPU_PPC_MPC8567 = 73
+    let UC_CPU_PPC_MPC8567E = 73
+    let UC_CPU_PPC_MPC8568 = 73
+    let UC_CPU_PPC_MPC8568E = 73
+    let UC_CPU_PPC_MPC8572 = 74
+    let UC_CPU_PPC_MPC8572E = 74
+    let UC_CPU_PPC_MPC8610 = 78
+    let UC_CPU_PPC_MPC8641 = 78
+    let UC_CPU_PPC_MPC8641D = 78
+
+    let UC_CPU_PPC64_620 = 0
+    let UC_CPU_PPC64_630 = 1
+    let UC_CPU_PPC64_631 = 2
+    let UC_CPU_PPC64_POWER4 = 3
+    let UC_CPU_PPC64_POWER4P = 4
+    let UC_CPU_PPC64_POWER5 = 5
+    let UC_CPU_PPC64_POWER5P_V21 = 6
+    let UC_CPU_PPC64_POWER6 = 7
+    let UC_CPU_PPC64_POWER_SERVER_MASK = 8
+    let UC_CPU_PPC64_POWER7_BASE = 9
+    let UC_CPU_PPC64_POWER7_V23 = 10
+    let UC_CPU_PPC64_POWER7P_BASE = 11
+    let UC_CPU_PPC64_POWER7P_V21 = 12
+    let UC_CPU_PPC64_POWER8E_BASE = 13
+    let UC_CPU_PPC64_POWER8E_V21 = 14
+    let UC_CPU_PPC64_POWER8_BASE = 15
+    let UC_CPU_PPC64_POWER8_V20 = 16
+    let UC_CPU_PPC64_POWER8NVL_BASE = 17
+    let UC_CPU_PPC64_POWER8NVL_V10 = 18
+    let UC_CPU_PPC64_POWER9_BASE = 19
+    let UC_CPU_PPC64_POWER9_DD1 = 20
+    let UC_CPU_PPC64_POWER9_DD20 = 21
+    let UC_CPU_PPC64_POWER10_BASE = 22
+    let UC_CPU_PPC64_POWER10_DD1 = 23
+    let UC_CPU_PPC64_970_V22 = 24
+    let UC_CPU_PPC64_970FX_V10 = 25
+    let UC_CPU_PPC64_970FX_V20 = 26
+    let UC_CPU_PPC64_970FX_V21 = 27
+    let UC_CPU_PPC64_970FX_V30 = 28
+    let UC_CPU_PPC64_970FX_V31 = 29
+    let UC_CPU_PPC64_970MP_V10 = 30
+    let UC_CPU_PPC64_970MP_V11 = 31
+    let UC_CPU_PPC64_CELL_V10 = 32
+    let UC_CPU_PPC64_CELL_V20 = 33
+    let UC_CPU_PPC64_CELL_V30 = 34
+    let UC_CPU_PPC64_CELL_V31 = 35
+    let UC_CPU_PPC64_RS64 = 36
+    let UC_CPU_PPC64_RS64II = 37
+    let UC_CPU_PPC64_RS64III = 38
+    let UC_CPU_PPC64_RS64IV = 39
+    let UC_CPU_PPC64_CELL_V32 = 35
+    let UC_CPU_PPC64_CELL = 35
+
     // PPC registers
 
     let UC_PPC_REG_INVALID = 0

bindings/dotnet/UnicornManaged/Const/Riscv.fs

@@ -7,6 +7,16 @@ open System
 [<AutoOpen>]
 module Riscv =
 
+    let UC_CPU_RISCV32_ANY = 0
+    let UC_CPU_RISCV32_BASE32 = 1
+    let UC_CPU_RISCV32_SIFIVE_E31 = 2
+    let UC_CPU_RISCV32_SIFIVE_U34 = 3
+
+    let UC_CPU_RISCV64_ANY = 0
+    let UC_CPU_RISCV64_BASE64 = 1
+    let UC_CPU_RISCV64_SIFIVE_E51 = 2
+    let UC_CPU_RISCV64_SIFIVE_U54 = 3
+
     // RISCV registers
 
     let UC_RISCV_REG_INVALID = 0

bindings/dotnet/UnicornManaged/Const/Sparc.fs

@@ -7,6 +7,38 @@ open System
 [<AutoOpen>]
 module Sparc =
 
+    let UC_CPU_SPARC_FUJITSU_MB86904 = 0
+    let UC_CPU_SPARC_FUJITSU_MB86907 = 1
+    let UC_CPU_SPARC_TI_MICROSPARC_I = 2
+    let UC_CPU_SPARC_TI_MICROSPARC_II = 3
+    let UC_CPU_SPARC_TI_MICROSPARC_IIEP = 4
+    let UC_CPU_SPARC_TI_SUPERSPARC_40 = 5
+    let UC_CPU_SPARC_TI_SUPERSPARC_50 = 6
+    let UC_CPU_SPARC_TI_SUPERSPARC_51 = 7
+    let UC_CPU_SPARC_TI_SUPERSPARC_60 = 8
+    let UC_CPU_SPARC_TI_SUPERSPARC_61 = 9
+    let UC_CPU_SPARC_TI_SUPERSPARC_II = 10
+    let UC_CPU_SPARC_LEON2 = 11
+    let UC_CPU_SPARC_LEON3 = 12
+
+    let UC_CPU_SPARC64_FUJITSU = 0
+    let UC_CPU_SPARC64_FUJITSU_III = 1
+    let UC_CPU_SPARC64_FUJITSU_IV = 2
+    let UC_CPU_SPARC64_FUJITSU_V = 3
+    let UC_CPU_SPARC64_TI_ULTRASPARC_I = 4
+    let UC_CPU_SPARC64_TI_ULTRASPARC_II = 5
+    let UC_CPU_SPARC64_TI_ULTRASPARC_III = 6
+    let UC_CPU_SPARC64_TI_ULTRASPARC_IIE = 7
+    let UC_CPU_SPARC64_SUN_ULTRASPARC_III = 8
+    let UC_CPU_SPARC64_SUN_ULTRASPARC_III_CU = 9
+    let UC_CPU_SPARC64_SUN_ULTRASPARC_IIII = 10
+    let UC_CPU_SPARC64_SUN_ULTRASPARC_IV = 11
+    let UC_CPU_SPARC64_SUN_ULTRASPARC_IV_PLUS = 12
+    let UC_CPU_SPARC64_SUN_ULTRASPARC_IIII_PLUS = 13
+    let UC_CPU_SPARC64_SUN_ULTRASPARC_T1 = 14
+    let UC_CPU_SPARC64_SUN_ULTRASPARC_T2 = 15
+    let UC_CPU_SPARC64_NEC_ULTRASPARC_I = 16
+
     // SPARC registers
 
     let UC_SPARC_REG_INVALID = 0

bindings/dotnet/UnicornManaged/Const/X86.fs

@@ -7,6 +7,45 @@ open System
 [<AutoOpen>]
 module X86 =
 
+    let UC_CPU_X86_QEMU64 = 0
+    let UC_CPU_X86_PHENOM = 1
+    let UC_CPU_X86_CORE2DUO = 2
+    let UC_CPU_X86_KVM64 = 3
+    let UC_CPU_X86_QEMU32 = 4
+    let UC_CPU_X86_KVM32 = 5
+    let UC_CPU_X86_COREDUO = 6
+    let UC_CPU_X86_486 = 7
+    let UC_CPU_X86_PENTIUM = 8
+    let UC_CPU_X86_PENTIUM2 = 9
+    let UC_CPU_X86_PENTIUM3 = 10
+    let UC_CPU_X86_ATHLON = 11
+    let UC_CPU_X86_N270 = 12
+    let UC_CPU_X86_CONROE = 13
+    let UC_CPU_X86_PENRYN = 14
+    let UC_CPU_X86_NEHALEM = 15
+    let UC_CPU_X86_WESTMERE = 16
+    let UC_CPU_X86_SANDYBRIDGE = 17
+    let UC_CPU_X86_IVYBRIDGE = 18
+    let UC_CPU_X86_HASWELL = 19
+    let UC_CPU_X86_BROADWELL = 20
+    let UC_CPU_X86_SKYLAKE_CLIENT = 21
+    let UC_CPU_X86_SKYLAKE_SERVER = 22
+    let UC_CPU_X86_CASCADELAKE_SERVER = 23
+    let UC_CPU_X86_COOPERLAKE = 24
+    let UC_CPU_X86_ICELAKE_CLIENT = 25
+    let UC_CPU_X86_ICELAKE_SERVER = 26
+    let UC_CPU_X86_DENVERTON = 27
+    let UC_CPU_X86_SNOWRIDGE = 28
+    let UC_CPU_X86_KNIGHTSMILL = 29
+    let UC_CPU_X86_OPTERON_G1 = 30
+    let UC_CPU_X86_OPTERON_G2 = 31
+    let UC_CPU_X86_OPTERON_G3 = 32
+    let UC_CPU_X86_OPTERON_G4 = 33
+    let UC_CPU_X86_OPTERON_G5 = 34
+    let UC_CPU_X86_EPYC = 35
+    let UC_CPU_X86_DHYANA = 36
+    let UC_CPU_X86_EPYC_ROME = 37
+
     // X86 registers
 
     let UC_X86_REG_INVALID = 0

bindings/go/Makefile

@@ -6,7 +6,7 @@ all: gen_const
 	cd unicorn && go build
 
 gen_const:
-	cd .. && python const_generator.py go
+	cd .. && python3 const_generator.py go
 
 test: all
 	cd unicorn && LD_LIBRARY_PATH=../../../ DYLD_LIBRARY_PATH=../../../ go test

bindings/go/unicorn/arm64_const.go

@@ -2,6 +2,11 @@ package unicorn
 // For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm64_const.go]
 const (
 
+	CPU_AARCH64_A57 = 0
+	CPU_AARCH64_A53 = 1
+	CPU_AARCH64_A72 = 2
+	CPU_AARCH64_MAX = 3
+
 // ARM64 registers
 
 	ARM64_REG_INVALID = 0

bindings/go/unicorn/arm_const.go

@@ -2,6 +2,40 @@ package unicorn
 // For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm_const.go]
 const (
 
+	CPU_ARM_926 = 0
+	CPU_ARM_946 = 1
+	CPU_ARM_1026 = 2
+	CPU_ARM_1136_R2 = 3
+	CPU_ARM_1136 = 4
+	CPU_ARM_1176 = 5
+	CPU_ARM_11MPCORE = 6
+	CPU_ARM_CORTEX_M0 = 7
+	CPU_ARM_CORTEX_M3 = 8
+	CPU_ARM_CORTEX_M4 = 9
+	CPU_ARM_CORTEX_M7 = 10
+	CPU_ARM_CORTEX_M33 = 11
+	CPU_ARM_CORTEX_R5 = 12
+	CPU_ARM_CORTEX_R5F = 13
+	CPU_ARM_CORTEX_A8 = 14
+	CPU_ARM_CORTEX_A9 = 15
+	CPU_ARM_CORTEX_A7 = 16
+	CPU_ARM_CORTEX_A15 = 17
+	CPU_ARM_TI925T = 18
+	CPU_ARM_SA1100 = 19
+	CPU_ARM_SA1110 = 20
+	CPU_ARM_PXA250 = 21
+	CPU_ARM_PXA255 = 22
+	CPU_ARM_PXA260 = 23
+	CPU_ARM_PXA261 = 24
+	CPU_ARM_PXA262 = 25
+	CPU_ARM_PXA270A0 = 26
+	CPU_ARM_PXA270A1 = 27
+	CPU_ARM_PXA270B0 = 28
+	CPU_ARM_PXA270B1 = 29
+	CPU_ARM_PXA270C0 = 30
+	CPU_ARM_PXA270C5 = 31
+	CPU_ARM_MAX = 32
+
 // ARM registers
 
 	ARM_REG_INVALID = 0

bindings/go/unicorn/m68k_const.go

@@ -2,6 +2,16 @@ package unicorn
 // For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [m68k_const.go]
 const (
 
+	CPU_M5206_CPU = 0
+	CPU_M68000_CPU = 1
+	CPU_M68020_CPU = 2
+	CPU_M68030_CPU = 3
+	CPU_M68040_CPU = 4
+	CPU_M68060_CPU = 5
+	CPU_M5208_CPU = 6
+	CPU_CFV4E_CPU = 7
+	CPU_ANY_CPU = 8
+
 // M68K registers
 
 	M68K_REG_INVALID = 0

bindings/go/unicorn/mips_const.go

@@ -2,6 +2,36 @@ package unicorn
 // For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [mips_const.go]
 const (
 
+	CPU_MIPS_4KC = 0
+	CPU_MIPS_4KM = 1
+	CPU_MIPS_4KECR1 = 2
+	CPU_MIPS_4KEMR1 = 3
+	CPU_MIPS_4KEC = 4
+	CPU_MIPS_4KEM = 5
+	CPU_MIPS_24KC = 6
+	CPU_MIPS_24KEC = 7
+	CPU_MIPS_24KF = 8
+	CPU_MIPS_34KF = 9
+	CPU_MIPS_74KF = 10
+	CPU_MIPS_M14K = 11
+	CPU_MIPS_M14KC = 12
+	CPU_MIPS_P5600 = 13
+	CPU_MIPS_MIPS32R6_GENERIC = 14
+	CPU_MIPS_I7200 = 15
+	CPU_MIPS_R4000 = 16
+	CPU_MIPS_VR5432 = 17
+	CPU_MIPS_5KC = 18
+	CPU_MIPS_5KF = 19
+	CPU_MIPS_20KC = 20
+	CPU_MIPS_MIPS64R2_GENERIC = 21
+	CPU_MIPS_5KEC = 22
+	CPU_MIPS_5KEF = 23
+	CPU_MIPS_I6400 = 24
+	CPU_MIPS_I6500 = 25
+	CPU_MIPS_LOONGSON_2E = 26
+	CPU_MIPS_LOONGSON_2F = 27
+	CPU_MIPS_MIPS64DSPR2 = 28
+
 // MIPS registers
 
 	MIPS_REG_INVALID = 0

bindings/go/unicorn/ppc_const.go

@@ -2,6 +2,307 @@ package unicorn
 // For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [ppc_const.go]
 const (
 
+	CPU_PPC_401A1 = 0
+	CPU_PPC_401B2 = 1
+	CPU_PPC_401C2 = 2
+	CPU_PPC_401D2 = 3
+	CPU_PPC_401E2 = 4
+	CPU_PPC_401F2 = 5
+	CPU_PPC_401G2 = 6
+	CPU_PPC_COBRA = 7
+	CPU_PPC_403GA = 8
+	CPU_PPC_403GB = 9
+	CPU_PPC_403GC = 10
+	CPU_PPC_403GCX = 11
+	CPU_PPC_405D2 = 12
+	CPU_PPC_405D4 = 13
+	CPU_PPC_405CRA = 14
+	CPU_PPC_405CRB = 15
+	CPU_PPC_405CRC = 16
+	CPU_PPC_405EP = 17
+	CPU_PPC_405EZ = 18
+	CPU_PPC_405GPA = 19
+	CPU_PPC_405GPB = 20
+	CPU_PPC_405GPC = 21
+	CPU_PPC_405GPD = 22
+	CPU_PPC_405GPR = 23
+	CPU_PPC_405LP = 24
+	CPU_PPC_NPE405H = 25
+	CPU_PPC_NPE405H2 = 26
+	CPU_PPC_NPE405L = 27
+	CPU_PPC_NPE4GS3 = 28
+	CPU_PPC_STB03 = 29
+	CPU_PPC_STB04 = 30
+	CPU_PPC_STB25 = 31
+	CPU_PPC_X2VP4 = 32
+	CPU_PPC_440_XILINX = 33
+	CPU_PPC_440EPA = 34
+	CPU_PPC_440EPB = 35
+	CPU_PPC_440GPB = 36
+	CPU_PPC_440GPC = 37
+	CPU_PPC_440GRX = 38
+	CPU_PPC_440GXA = 39
+	CPU_PPC_440GXB = 40
+	CPU_PPC_440GXC = 41
+	CPU_PPC_440GXF = 42
+	CPU_PPC_440SP = 43
+	CPU_PPC_440SP2 = 44
+	CPU_PPC_440SPE = 45
+	CPU_PPC_460EXB = 46
+	CPU_PPC_MPC5XX = 47
+	CPU_PPC_MPC8XX = 48
+	CPU_PPC_G2 = 49
+	CPU_PPC_G2H4 = 50
+	CPU_PPC_G2GP = 51
+	CPU_PPC_G2LS = 52
+	CPU_PPC_MPC603 = 53
+	CPU_PPC_G2_HIP3 = 54
+	CPU_PPC_G2_HIP4 = 55
+	CPU_PPC_G2LE = 56
+	CPU_PPC_G2LEGP = 57
+	CPU_PPC_G2LELS = 58
+	CPU_PPC_G2LEGP1 = 59
+	CPU_PPC_G2LEGP3 = 60
+	CPU_PPC_E200Z5 = 61
+	CPU_PPC_E200Z6 = 62
+	CPU_PPC_E300C1 = 63
+	CPU_PPC_E300C2 = 64
+	CPU_PPC_E300C3 = 65
+	CPU_PPC_E300C4 = 66
+	CPU_PPC_E500V1_V10 = 67
+	CPU_PPC_E500V1_V20 = 68
+	CPU_PPC_E500V2_V10 = 69
+	CPU_PPC_E500V2_V11 = 70
+	CPU_PPC_E500V2_V20 = 71
+	CPU_PPC_E500V2_V21 = 72
+	CPU_PPC_E500V2_V22 = 73
+	CPU_PPC_E500V2_V30 = 74
+	CPU_PPC_E500MC = 75
+	CPU_PPC_E5500 = 76
+	CPU_PPC_E6500 = 77
+	CPU_PPC_E600 = 78
+	CPU_PPC_601_V0 = 79
+	CPU_PPC_601_V1 = 80
+	CPU_PPC_601_V2 = 81
+	CPU_PPC_602 = 82
+	CPU_PPC_603 = 83
+	CPU_PPC_603E_V11 = 84
+	CPU_PPC_603E_V12 = 85
+	CPU_PPC_603E_V13 = 86
+	CPU_PPC_603E_V14 = 87
+	CPU_PPC_603E_V22 = 88
+	CPU_PPC_603E_V3 = 89
+	CPU_PPC_603E_V4 = 90
+	CPU_PPC_603E_V41 = 91
+	CPU_PPC_603E7T = 92
+	CPU_PPC_603E7V = 93
+	CPU_PPC_603E7V1 = 94
+	CPU_PPC_603E7V2 = 95
+	CPU_PPC_603E7 = 96
+	CPU_PPC_603P = 97
+	CPU_PPC_604 = 98
+	CPU_PPC_604E_V10 = 99
+	CPU_PPC_604E_V22 = 100
+	CPU_PPC_604E_V24 = 101
+	CPU_PPC_604R = 102
+	CPU_PPC_7X0_V10 = 103
+	CPU_PPC_7X0_V20 = 104
+	CPU_PPC_7X0_V21 = 105
+	CPU_PPC_7X0_V22 = 106
+	CPU_PPC_7X0_V30 = 107
+	CPU_PPC_7X0_V31 = 108
+	CPU_PPC_740E = 109
+	CPU_PPC_750E = 110
+	CPU_PPC_7X0P = 111
+	CPU_PPC_750CL_V10 = 112
+	CPU_PPC_750CL_V20 = 113
+	CPU_PPC_750CX_V10 = 114
+	CPU_PPC_750CX_V20 = 115
+	CPU_PPC_750CX_V21 = 116
+	CPU_PPC_750CX_V22 = 117
+	CPU_PPC_750CXE_V21 = 118
+	CPU_PPC_750CXE_V22 = 119
+	CPU_PPC_750CXE_V23 = 120
+	CPU_PPC_750CXE_V24 = 121
+	CPU_PPC_750CXE_V24B = 122
+	CPU_PPC_750CXE_V30 = 123
+	CPU_PPC_750CXE_V31 = 124
+	CPU_PPC_750CXE_V31B = 125
+	CPU_PPC_750CXR = 126
+	CPU_PPC_750FL = 127
+	CPU_PPC_750FX_V10 = 128
+	CPU_PPC_750FX_V20 = 129
+	CPU_PPC_750FX_V21 = 130
+	CPU_PPC_750FX_V22 = 131
+	CPU_PPC_750FX_V23 = 132
+	CPU_PPC_750GL = 133
+	CPU_PPC_750GX_V10 = 134
+	CPU_PPC_750GX_V11 = 135
+	CPU_PPC_750GX_V12 = 136
+	CPU_PPC_750L_V20 = 137
+	CPU_PPC_750L_V21 = 138
+	CPU_PPC_750L_V22 = 139
+	CPU_PPC_750L_V30 = 140
+	CPU_PPC_750L_V32 = 141
+	CPU_PPC_7X5_V10 = 142
+	CPU_PPC_7X5_V11 = 143
+	CPU_PPC_7X5_V20 = 144
+	CPU_PPC_7X5_V21 = 145
+	CPU_PPC_7X5_V22 = 146
+	CPU_PPC_7X5_V23 = 147
+	CPU_PPC_7X5_V24 = 148
+	CPU_PPC_7X5_V25 = 149
+	CPU_PPC_7X5_V26 = 150
+	CPU_PPC_7X5_V27 = 151
+	CPU_PPC_7X5_V28 = 152
+	CPU_PPC_7400_V10 = 153
+	CPU_PPC_7400_V11 = 154
+	CPU_PPC_7400_V20 = 155
+	CPU_PPC_7400_V21 = 156
+	CPU_PPC_7400_V22 = 157
+	CPU_PPC_7400_V26 = 158
+	CPU_PPC_7400_V27 = 159
+	CPU_PPC_7400_V28 = 160
+	CPU_PPC_7400_V29 = 161
+	CPU_PPC_7410_V10 = 162
+	CPU_PPC_7410_V11 = 163
+	CPU_PPC_7410_V12 = 164
+	CPU_PPC_7410_V13 = 165
+	CPU_PPC_7410_V14 = 166
+	CPU_PPC_7448_V10 = 167
+	CPU_PPC_7448_V11 = 168
+	CPU_PPC_7448_V20 = 169
+	CPU_PPC_7448_V21 = 170
+	CPU_PPC_7450_V10 = 171
+	CPU_PPC_7450_V11 = 172
+	CPU_PPC_7450_V12 = 173
+	CPU_PPC_7450_V20 = 174
+	CPU_PPC_7450_V21 = 175
+	CPU_PPC_74X1_V23 = 176
+	CPU_PPC_74X1_V210 = 177
+	CPU_PPC_74X5_V10 = 178
+	CPU_PPC_74X5_V21 = 179
+	CPU_PPC_74X5_V32 = 180
+	CPU_PPC_74X5_V33 = 181
+	CPU_PPC_74X5_V34 = 182
+	CPU_PPC_74X7_V10 = 183
+	CPU_PPC_74X7_V11 = 184
+	CPU_PPC_74X7_V12 = 185
+	CPU_PPC_74X7A_V10 = 186
+	CPU_PPC_74X7A_V11 = 187
+	CPU_PPC_74X7A_V12 = 188
+	CPU_PPC_IOP480 = 1
+	CPU_PPC_X2VP20 = 42
+	CPU_PPC_440GRA = 35
+	CPU_PPC_440EPX = 38
+	CPU_PPC_MPC5200_V10 = 59
+	CPU_PPC_MPC5200_V11 = 59
+	CPU_PPC_MPC5200_V12 = 59
+	CPU_PPC_MPC5200B_V20 = 59
+	CPU_PPC_MPC5200B_V21 = 59
+	CPU_PPC_MPC834X = 63
+	CPU_PPC_MPC837X = 66
+	CPU_PPC_E500 = 73
+	CPU_PPC_MPC8533_V10 = 72
+	CPU_PPC_MPC8533_V11 = 73
+	CPU_PPC_MPC8533E_V10 = 72
+	CPU_PPC_MPC8533E_V11 = 73
+	CPU_PPC_MPC8540_V10 = 67
+	CPU_PPC_MPC8540_V20 = 68
+	CPU_PPC_MPC8540_V21 = 68
+	CPU_PPC_MPC8541_V10 = 68
+	CPU_PPC_MPC8541_V11 = 68
+	CPU_PPC_MPC8541E_V10 = 68
+	CPU_PPC_MPC8541E_V11 = 68
+	CPU_PPC_MPC8543_V10 = 69
+	CPU_PPC_MPC8543_V11 = 70
+	CPU_PPC_MPC8543_V20 = 71
+	CPU_PPC_MPC8543_V21 = 72
+	CPU_PPC_MPC8543E_V10 = 69
+	CPU_PPC_MPC8543E_V11 = 70
+	CPU_PPC_MPC8543E_V20 = 71
+	CPU_PPC_MPC8543E_V21 = 72
+	CPU_PPC_MPC8544_V10 = 72
+	CPU_PPC_MPC8544_V11 = 73
+	CPU_PPC_MPC8544E_V11 = 73
+	CPU_PPC_MPC8544E_V10 = 72
+	CPU_PPC_MPC8545_V10 = 69
+	CPU_PPC_MPC8545_V20 = 71
+	CPU_PPC_MPC8545_V21 = 72
+	CPU_PPC_MPC8545E_V10 = 69
+	CPU_PPC_MPC8545E_V20 = 71
+	CPU_PPC_MPC8545E_V21 = 72
+	CPU_PPC_MPC8547E_V10 = 69
+	CPU_PPC_MPC8547E_V20 = 71
+	CPU_PPC_MPC8547E_V21 = 72
+	CPU_PPC_MPC8548_V10 = 69
+	CPU_PPC_MPC8548_V11 = 70
+	CPU_PPC_MPC8548_V20 = 71
+	CPU_PPC_MPC8548_V21 = 72
+	CPU_PPC_MPC8548E_V10 = 69
+	CPU_PPC_MPC8548E_V11 = 70
+	CPU_PPC_MPC8548E_V20 = 71
+	CPU_PPC_MPC8548E_V21 = 72
+	CPU_PPC_MPC8555_V10 = 69
+	CPU_PPC_MPC8555_V11 = 70
+	CPU_PPC_MPC8555E_V10 = 69
+	CPU_PPC_MPC8555E_V11 = 70
+	CPU_PPC_MPC8560_V10 = 69
+	CPU_PPC_MPC8560_V20 = 71
+	CPU_PPC_MPC8560_V21 = 72
+	CPU_PPC_MPC8567 = 73
+	CPU_PPC_MPC8567E = 73
+	CPU_PPC_MPC8568 = 73
+	CPU_PPC_MPC8568E = 73
+	CPU_PPC_MPC8572 = 74
+	CPU_PPC_MPC8572E = 74
+	CPU_PPC_MPC8610 = 78
+	CPU_PPC_MPC8641 = 78
+	CPU_PPC_MPC8641D = 78
+
+	CPU_PPC64_620 = 0
+	CPU_PPC64_630 = 1
+	CPU_PPC64_631 = 2
+	CPU_PPC64_POWER4 = 3
+	CPU_PPC64_POWER4P = 4
+	CPU_PPC64_POWER5 = 5
+	CPU_PPC64_POWER5P_V21 = 6
+	CPU_PPC64_POWER6 = 7
+	CPU_PPC64_POWER_SERVER_MASK = 8
+	CPU_PPC64_POWER7_BASE = 9
+	CPU_PPC64_POWER7_V23 = 10
+	CPU_PPC64_POWER7P_BASE = 11
+	CPU_PPC64_POWER7P_V21 = 12
+	CPU_PPC64_POWER8E_BASE = 13
+	CPU_PPC64_POWER8E_V21 = 14
+	CPU_PPC64_POWER8_BASE = 15
+	CPU_PPC64_POWER8_V20 = 16
+	CPU_PPC64_POWER8NVL_BASE = 17
+	CPU_PPC64_POWER8NVL_V10 = 18
+	CPU_PPC64_POWER9_BASE = 19
+	CPU_PPC64_POWER9_DD1 = 20
+	CPU_PPC64_POWER9_DD20 = 21
+	CPU_PPC64_POWER10_BASE = 22
+	CPU_PPC64_POWER10_DD1 = 23
+	CPU_PPC64_970_V22 = 24
+	CPU_PPC64_970FX_V10 = 25
+	CPU_PPC64_970FX_V20 = 26
+	CPU_PPC64_970FX_V21 = 27
+	CPU_PPC64_970FX_V30 = 28
+	CPU_PPC64_970FX_V31 = 29
+	CPU_PPC64_970MP_V10 = 30
+	CPU_PPC64_970MP_V11 = 31
+	CPU_PPC64_CELL_V10 = 32
+	CPU_PPC64_CELL_V20 = 33
+	CPU_PPC64_CELL_V30 = 34
+	CPU_PPC64_CELL_V31 = 35
+	CPU_PPC64_RS64 = 36
+	CPU_PPC64_RS64II = 37
+	CPU_PPC64_RS64III = 38
+	CPU_PPC64_RS64IV = 39
+	CPU_PPC64_CELL_V32 = 35
+	CPU_PPC64_CELL = 35
+
 // PPC registers
 
 	PPC_REG_INVALID = 0

bindings/go/unicorn/riscv_const.go

@@ -2,6 +2,16 @@ package unicorn
 // For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [riscv_const.go]
 const (
 
+	CPU_RISCV32_ANY = 0
+	CPU_RISCV32_BASE32 = 1
+	CPU_RISCV32_SIFIVE_E31 = 2
+	CPU_RISCV32_SIFIVE_U34 = 3
+
+	CPU_RISCV64_ANY = 0
+	CPU_RISCV64_BASE64 = 1
+	CPU_RISCV64_SIFIVE_E51 = 2
+	CPU_RISCV64_SIFIVE_U54 = 3
+
 // RISCV registers
 
 	RISCV_REG_INVALID = 0

bindings/go/unicorn/sparc_const.go

@@ -2,6 +2,38 @@ package unicorn
 // For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [sparc_const.go]
 const (
 
+	CPU_SPARC_FUJITSU_MB86904 = 0
+	CPU_SPARC_FUJITSU_MB86907 = 1
+	CPU_SPARC_TI_MICROSPARC_I = 2
+	CPU_SPARC_TI_MICROSPARC_II = 3
+	CPU_SPARC_TI_MICROSPARC_IIEP = 4
+	CPU_SPARC_TI_SUPERSPARC_40 = 5
+	CPU_SPARC_TI_SUPERSPARC_50 = 6
+	CPU_SPARC_TI_SUPERSPARC_51 = 7
+	CPU_SPARC_TI_SUPERSPARC_60 = 8
+	CPU_SPARC_TI_SUPERSPARC_61 = 9
+	CPU_SPARC_TI_SUPERSPARC_II = 10
+	CPU_SPARC_LEON2 = 11
+	CPU_SPARC_LEON3 = 12
+
+	CPU_SPARC64_FUJITSU = 0
+	CPU_SPARC64_FUJITSU_III = 1
+	CPU_SPARC64_FUJITSU_IV = 2
+	CPU_SPARC64_FUJITSU_V = 3
+	CPU_SPARC64_TI_ULTRASPARC_I = 4
+	CPU_SPARC64_TI_ULTRASPARC_II = 5
+	CPU_SPARC64_TI_ULTRASPARC_III = 6
+	CPU_SPARC64_TI_ULTRASPARC_IIE = 7
+	CPU_SPARC64_SUN_ULTRASPARC_III = 8
+	CPU_SPARC64_SUN_ULTRASPARC_III_CU = 9
+	CPU_SPARC64_SUN_ULTRASPARC_IIII = 10
+	CPU_SPARC64_SUN_ULTRASPARC_IV = 11
+	CPU_SPARC64_SUN_ULTRASPARC_IV_PLUS = 12
+	CPU_SPARC64_SUN_ULTRASPARC_IIII_PLUS = 13
+	CPU_SPARC64_SUN_ULTRASPARC_T1 = 14
+	CPU_SPARC64_SUN_ULTRASPARC_T2 = 15
+	CPU_SPARC64_NEC_ULTRASPARC_I = 16
+
 // SPARC registers
 
 	SPARC_REG_INVALID = 0

bindings/go/unicorn/unicorn_const.go

@@ -107,6 +107,22 @@ const (
 	QUERY_ARCH = 3
 	QUERY_TIMEOUT = 4
 
+	CTL_IO_NONE = 0
+	CTL_IO_WRITE = 1
+	CTL_IO_READ = 2
+	CTL_IO_READ_WRITE = 3
+
+	CTL_UC_MODE = 0
+	CTL_UC_PAGE_SIZE = 1
+	CTL_UC_ARCH = 2
+	CTL_UC_TIMEOUT = 3
+	CTL_UC_EXITS_CNT = 4
+	CTL_UC_EXITS = 5
+	CTL_CPU_MODEL = 6
+	CTL_TB_EDGE = 7
+	CTL_TB_REQUEST_CACHE = 8
+	CTL_TB_REMOVE_CACHE = 9
+
 	PROT_NONE = 0
 	PROT_READ = 1
 	PROT_WRITE = 2

bindings/go/unicorn/x86_const.go

@@ -2,6 +2,45 @@ package unicorn
 // For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [x86_const.go]
 const (
 
+	CPU_X86_QEMU64 = 0
+	CPU_X86_PHENOM = 1
+	CPU_X86_CORE2DUO = 2
+	CPU_X86_KVM64 = 3
+	CPU_X86_QEMU32 = 4
+	CPU_X86_KVM32 = 5
+	CPU_X86_COREDUO = 6
+	CPU_X86_486 = 7
+	CPU_X86_PENTIUM = 8
+	CPU_X86_PENTIUM2 = 9
+	CPU_X86_PENTIUM3 = 10
+	CPU_X86_ATHLON = 11
+	CPU_X86_N270 = 12
+	CPU_X86_CONROE = 13
+	CPU_X86_PENRYN = 14
+	CPU_X86_NEHALEM = 15
+	CPU_X86_WESTMERE = 16
+	CPU_X86_SANDYBRIDGE = 17
+	CPU_X86_IVYBRIDGE = 18
+	CPU_X86_HASWELL = 19
+	CPU_X86_BROADWELL = 20
+	CPU_X86_SKYLAKE_CLIENT = 21
+	CPU_X86_SKYLAKE_SERVER = 22
+	CPU_X86_CASCADELAKE_SERVER = 23
+	CPU_X86_COOPERLAKE = 24
+	CPU_X86_ICELAKE_CLIENT = 25
+	CPU_X86_ICELAKE_SERVER = 26
+	CPU_X86_DENVERTON = 27
+	CPU_X86_SNOWRIDGE = 28
+	CPU_X86_KNIGHTSMILL = 29
+	CPU_X86_OPTERON_G1 = 30
+	CPU_X86_OPTERON_G2 = 31
+	CPU_X86_OPTERON_G3 = 32
+	CPU_X86_OPTERON_G4 = 33
+	CPU_X86_OPTERON_G5 = 34
+	CPU_X86_EPYC = 35
+	CPU_X86_DHYANA = 36
+	CPU_X86_EPYC_ROME = 37
+
 // X86 registers
 
 	X86_REG_INVALID = 0

bindings/java/Makefile

@@ -19,7 +19,7 @@ uninstall:
 	$(MAKE) -f Makefile.build uninstall
 
 gen_const:
-	cd .. && python const_generator.py java
+	cd .. && python3 const_generator.py java
 
 clean:
 	rm -f unicorn/*.class

bindings/java/unicorn/Arm64Const.java

@@ -4,6 +4,11 @@ package unicorn;
 
 public interface Arm64Const {
 
+   public static final int UC_CPU_AARCH64_A57 = 0;
+   public static final int UC_CPU_AARCH64_A53 = 1;
+   public static final int UC_CPU_AARCH64_A72 = 2;
+   public static final int UC_CPU_AARCH64_MAX = 3;
+
 // ARM64 registers
 
    public static final int UC_ARM64_REG_INVALID = 0;

bindings/java/unicorn/ArmConst.java

@@ -4,6 +4,40 @@ package unicorn;
 
 public interface ArmConst {
 
+   public static final int UC_CPU_ARM_926 = 0;
+   public static final int UC_CPU_ARM_946 = 1;
+   public static final int UC_CPU_ARM_1026 = 2;
+   public static final int UC_CPU_ARM_1136_R2 = 3;
+   public static final int UC_CPU_ARM_1136 = 4;
+   public static final int UC_CPU_ARM_1176 = 5;
+   public static final int UC_CPU_ARM_11MPCORE = 6;
+   public static final int UC_CPU_ARM_CORTEX_M0 = 7;
+   public static final int UC_CPU_ARM_CORTEX_M3 = 8;
+   public static final int UC_CPU_ARM_CORTEX_M4 = 9;
+   public static final int UC_CPU_ARM_CORTEX_M7 = 10;
+   public static final int UC_CPU_ARM_CORTEX_M33 = 11;
+   public static final int UC_CPU_ARM_CORTEX_R5 = 12;
+   public static final int UC_CPU_ARM_CORTEX_R5F = 13;
+   public static final int UC_CPU_ARM_CORTEX_A8 = 14;
+   public static final int UC_CPU_ARM_CORTEX_A9 = 15;
+   public static final int UC_CPU_ARM_CORTEX_A7 = 16;
+   public static final int UC_CPU_ARM_CORTEX_A15 = 17;
+   public static final int UC_CPU_ARM_TI925T = 18;
+   public static final int UC_CPU_ARM_SA1100 = 19;
+   public static final int UC_CPU_ARM_SA1110 = 20;
+   public static final int UC_CPU_ARM_PXA250 = 21;
+   public static final int UC_CPU_ARM_PXA255 = 22;
+   public static final int UC_CPU_ARM_PXA260 = 23;
+   public static final int UC_CPU_ARM_PXA261 = 24;
+   public static final int UC_CPU_ARM_PXA262 = 25;
+   public static final int UC_CPU_ARM_PXA270A0 = 26;
+   public static final int UC_CPU_ARM_PXA270A1 = 27;
+   public static final int UC_CPU_ARM_PXA270B0 = 28;
+   public static final int UC_CPU_ARM_PXA270B1 = 29;
+   public static final int UC_CPU_ARM_PXA270C0 = 30;
+   public static final int UC_CPU_ARM_PXA270C5 = 31;
+   public static final int UC_CPU_ARM_MAX = 32;
+
 // ARM registers
 
    public static final int UC_ARM_REG_INVALID = 0;

bindings/java/unicorn/M68kConst.java

@@ -4,6 +4,16 @@ package unicorn;
 
 public interface M68kConst {
 
+   public static final int UC_CPU_M5206_CPU = 0;
+   public static final int UC_CPU_M68000_CPU = 1;
+   public static final int UC_CPU_M68020_CPU = 2;
+   public static final int UC_CPU_M68030_CPU = 3;
+   public static final int UC_CPU_M68040_CPU = 4;
+   public static final int UC_CPU_M68060_CPU = 5;
+   public static final int UC_CPU_M5208_CPU = 6;
+   public static final int UC_CPU_CFV4E_CPU = 7;
+   public static final int UC_CPU_ANY_CPU = 8;
+
 // M68K registers
 
    public static final int UC_M68K_REG_INVALID = 0;

bindings/java/unicorn/MipsConst.java

@@ -4,6 +4,36 @@ package unicorn;
 
 public interface MipsConst {
 
+   public static final int UC_CPU_MIPS_4KC = 0;
+   public static final int UC_CPU_MIPS_4KM = 1;
+   public static final int UC_CPU_MIPS_4KECR1 = 2;
+   public static final int UC_CPU_MIPS_4KEMR1 = 3;
+   public static final int UC_CPU_MIPS_4KEC = 4;
+   public static final int UC_CPU_MIPS_4KEM = 5;
+   public static final int UC_CPU_MIPS_24KC = 6;
+   public static final int UC_CPU_MIPS_24KEC = 7;
+   public static final int UC_CPU_MIPS_24KF = 8;
+   public static final int UC_CPU_MIPS_34KF = 9;
+   public static final int UC_CPU_MIPS_74KF = 10;
+   public static final int UC_CPU_MIPS_M14K = 11;
+   public static final int UC_CPU_MIPS_M14KC = 12;
+   public static final int UC_CPU_MIPS_P5600 = 13;
+   public static final int UC_CPU_MIPS_MIPS32R6_GENERIC = 14;
+   public static final int UC_CPU_MIPS_I7200 = 15;
+   public static final int UC_CPU_MIPS_R4000 = 16;
+   public static final int UC_CPU_MIPS_VR5432 = 17;
+   public static final int UC_CPU_MIPS_5KC = 18;
+   public static final int UC_CPU_MIPS_5KF = 19;
+   public static final int UC_CPU_MIPS_20KC = 20;
+   public static final int UC_CPU_MIPS_MIPS64R2_GENERIC = 21;
+   public static final int UC_CPU_MIPS_5KEC = 22;
+   public static final int UC_CPU_MIPS_5KEF = 23;
+   public static final int UC_CPU_MIPS_I6400 = 24;
+   public static final int UC_CPU_MIPS_I6500 = 25;
+   public static final int UC_CPU_MIPS_LOONGSON_2E = 26;
+   public static final int UC_CPU_MIPS_LOONGSON_2F = 27;
+   public static final int UC_CPU_MIPS_MIPS64DSPR2 = 28;
+
 // MIPS registers
 
    public static final int UC_MIPS_REG_INVALID = 0;

bindings/java/unicorn/PpcConst.java

@@ -4,6 +4,307 @@ package unicorn;
 
 public interface PpcConst {
 
+   public static final int UC_CPU_PPC_401A1 = 0;
+   public static final int UC_CPU_PPC_401B2 = 1;
+   public static final int UC_CPU_PPC_401C2 = 2;
+   public static final int UC_CPU_PPC_401D2 = 3;
+   public static final int UC_CPU_PPC_401E2 = 4;
+   public static final int UC_CPU_PPC_401F2 = 5;
+   public static final int UC_CPU_PPC_401G2 = 6;
+   public static final int UC_CPU_PPC_COBRA = 7;
+   public static final int UC_CPU_PPC_403GA = 8;
+   public static final int UC_CPU_PPC_403GB = 9;
+   public static final int UC_CPU_PPC_403GC = 10;
+   public static final int UC_CPU_PPC_403GCX = 11;
+   public static final int UC_CPU_PPC_405D2 = 12;
+   public static final int UC_CPU_PPC_405D4 = 13;
+   public static final int UC_CPU_PPC_405CRA = 14;
+   public static final int UC_CPU_PPC_405CRB = 15;
+   public static final int UC_CPU_PPC_405CRC = 16;
+   public static final int UC_CPU_PPC_405EP = 17;
+   public static final int UC_CPU_PPC_405EZ = 18;
+   public static final int UC_CPU_PPC_405GPA = 19;
+   public static final int UC_CPU_PPC_405GPB = 20;
+   public static final int UC_CPU_PPC_405GPC = 21;
+   public static final int UC_CPU_PPC_405GPD = 22;
+   public static final int UC_CPU_PPC_405GPR = 23;
+   public static final int UC_CPU_PPC_405LP = 24;
+   public static final int UC_CPU_PPC_NPE405H = 25;
+   public static final int UC_CPU_PPC_NPE405H2 = 26;
+   public static final int UC_CPU_PPC_NPE405L = 27;
+   public static final int UC_CPU_PPC_NPE4GS3 = 28;
+   public static final int UC_CPU_PPC_STB03 = 29;
+   public static final int UC_CPU_PPC_STB04 = 30;
+   public static final int UC_CPU_PPC_STB25 = 31;
+   public static final int UC_CPU_PPC_X2VP4 = 32;
+   public static final int UC_CPU_PPC_440_XILINX = 33;
+   public static final int UC_CPU_PPC_440EPA = 34;
+   public static final int UC_CPU_PPC_440EPB = 35;
+   public static final int UC_CPU_PPC_440GPB = 36;
+   public static final int UC_CPU_PPC_440GPC = 37;
+   public static final int UC_CPU_PPC_440GRX = 38;
+   public static final int UC_CPU_PPC_440GXA = 39;
+   public static final int UC_CPU_PPC_440GXB = 40;
+   public static final int UC_CPU_PPC_440GXC = 41;
+   public static final int UC_CPU_PPC_440GXF = 42;
+   public static final int UC_CPU_PPC_440SP = 43;
+   public static final int UC_CPU_PPC_440SP2 = 44;
+   public static final int UC_CPU_PPC_440SPE = 45;
+   public static final int UC_CPU_PPC_460EXB = 46;
+   public static final int UC_CPU_PPC_MPC5XX = 47;
+   public static final int UC_CPU_PPC_MPC8XX = 48;
+   public static final int UC_CPU_PPC_G2 = 49;
+   public static final int UC_CPU_PPC_G2H4 = 50;
+   public static final int UC_CPU_PPC_G2GP = 51;
+   public static final int UC_CPU_PPC_G2LS = 52;
+   public static final int UC_CPU_PPC_MPC603 = 53;
+   public static final int UC_CPU_PPC_G2_HIP3 = 54;
+   public static final int UC_CPU_PPC_G2_HIP4 = 55;
+   public static final int UC_CPU_PPC_G2LE = 56;
+   public static final int UC_CPU_PPC_G2LEGP = 57;
+   public static final int UC_CPU_PPC_G2LELS = 58;
+   public static final int UC_CPU_PPC_G2LEGP1 = 59;
+   public static final int UC_CPU_PPC_G2LEGP3 = 60;
+   public static final int UC_CPU_PPC_E200Z5 = 61;
+   public static final int UC_CPU_PPC_E200Z6 = 62;
+   public static final int UC_CPU_PPC_E300C1 = 63;
+   public static final int UC_CPU_PPC_E300C2 = 64;
+   public static final int UC_CPU_PPC_E300C3 = 65;
+   public static final int UC_CPU_PPC_E300C4 = 66;
+   public static final int UC_CPU_PPC_E500V1_V10 = 67;
+   public static final int UC_CPU_PPC_E500V1_V20 = 68;
+   public static final int UC_CPU_PPC_E500V2_V10 = 69;
+   public static final int UC_CPU_PPC_E500V2_V11 = 70;
+   public static final int UC_CPU_PPC_E500V2_V20 = 71;
+   public static final int UC_CPU_PPC_E500V2_V21 = 72;
+   public static final int UC_CPU_PPC_E500V2_V22 = 73;
+   public static final int UC_CPU_PPC_E500V2_V30 = 74;
+   public static final int UC_CPU_PPC_E500MC = 75;
+   public static final int UC_CPU_PPC_E5500 = 76;
+   public static final int UC_CPU_PPC_E6500 = 77;
+   public static final int UC_CPU_PPC_E600 = 78;
+   public static final int UC_CPU_PPC_601_V0 = 79;
+   public static final int UC_CPU_PPC_601_V1 = 80;
+   public static final int UC_CPU_PPC_601_V2 = 81;
+   public static final int UC_CPU_PPC_602 = 82;
+   public static final int UC_CPU_PPC_603 = 83;
+   public static final int UC_CPU_PPC_603E_V11 = 84;
+   public static final int UC_CPU_PPC_603E_V12 = 85;
+   public static final int UC_CPU_PPC_603E_V13 = 86;
+   public static final int UC_CPU_PPC_603E_V14 = 87;
+   public static final int UC_CPU_PPC_603E_V22 = 88;
+   public static final int UC_CPU_PPC_603E_V3 = 89;
+   public static final int UC_CPU_PPC_603E_V4 = 90;
+   public static final int UC_CPU_PPC_603E_V41 = 91;
+   public static final int UC_CPU_PPC_603E7T = 92;
+   public static final int UC_CPU_PPC_603E7V = 93;
+   public static final int UC_CPU_PPC_603E7V1 = 94;
+   public static final int UC_CPU_PPC_603E7V2 = 95;
+   public static final int UC_CPU_PPC_603E7 = 96;
+   public static final int UC_CPU_PPC_603P = 97;
+   public static final int UC_CPU_PPC_604 = 98;
+   public static final int UC_CPU_PPC_604E_V10 = 99;
+   public static final int UC_CPU_PPC_604E_V22 = 100;
+   public static final int UC_CPU_PPC_604E_V24 = 101;
+   public static final int UC_CPU_PPC_604R = 102;
+   public static final int UC_CPU_PPC_7X0_V10 = 103;
+   public static final int UC_CPU_PPC_7X0_V20 = 104;
+   public static final int UC_CPU_PPC_7X0_V21 = 105;
+   public static final int UC_CPU_PPC_7X0_V22 = 106;
+   public static final int UC_CPU_PPC_7X0_V30 = 107;
+   public static final int UC_CPU_PPC_7X0_V31 = 108;
+   public static final int UC_CPU_PPC_740E = 109;
+   public static final int UC_CPU_PPC_750E = 110;
+   public static final int UC_CPU_PPC_7X0P = 111;
+   public static final int UC_CPU_PPC_750CL_V10 = 112;
+   public static final int UC_CPU_PPC_750CL_V20 = 113;
+   public static final int UC_CPU_PPC_750CX_V10 = 114;
+   public static final int UC_CPU_PPC_750CX_V20 = 115;
+   public static final int UC_CPU_PPC_750CX_V21 = 116;
+   public static final int UC_CPU_PPC_750CX_V22 = 117;
+   public static final int UC_CPU_PPC_750CXE_V21 = 118;
+   public static final int UC_CPU_PPC_750CXE_V22 = 119;
+   public static final int UC_CPU_PPC_750CXE_V23 = 120;
+   public static final int UC_CPU_PPC_750CXE_V24 = 121;
+   public static final int UC_CPU_PPC_750CXE_V24B = 122;
+   public static final int UC_CPU_PPC_750CXE_V30 = 123;
+   public static final int UC_CPU_PPC_750CXE_V31 = 124;
+   public static final int UC_CPU_PPC_750CXE_V31B = 125;
+   public static final int UC_CPU_PPC_750CXR = 126;
+   public static final int UC_CPU_PPC_750FL = 127;
+   public static final int UC_CPU_PPC_750FX_V10 = 128;
+   public static final int UC_CPU_PPC_750FX_V20 = 129;
+   public static final int UC_CPU_PPC_750FX_V21 = 130;
+   public static final int UC_CPU_PPC_750FX_V22 = 131;
+   public static final int UC_CPU_PPC_750FX_V23 = 132;
+   public static final int UC_CPU_PPC_750GL = 133;
+   public static final int UC_CPU_PPC_750GX_V10 = 134;
+   public static final int UC_CPU_PPC_750GX_V11 = 135;
+   public static final int UC_CPU_PPC_750GX_V12 = 136;
+   public static final int UC_CPU_PPC_750L_V20 = 137;
+   public static final int UC_CPU_PPC_750L_V21 = 138;
+   public static final int UC_CPU_PPC_750L_V22 = 139;
+   public static final int UC_CPU_PPC_750L_V30 = 140;
+   public static final int UC_CPU_PPC_750L_V32 = 141;
+   public static final int UC_CPU_PPC_7X5_V10 = 142;
+   public static final int UC_CPU_PPC_7X5_V11 = 143;
+   public static final int UC_CPU_PPC_7X5_V20 = 144;
+   public static final int UC_CPU_PPC_7X5_V21 = 145;
+   public static final int UC_CPU_PPC_7X5_V22 = 146;
+   public static final int UC_CPU_PPC_7X5_V23 = 147;
+   public static final int UC_CPU_PPC_7X5_V24 = 148;
+   public static final int UC_CPU_PPC_7X5_V25 = 149;
+   public static final int UC_CPU_PPC_7X5_V26 = 150;
+   public static final int UC_CPU_PPC_7X5_V27 = 151;
+   public static final int UC_CPU_PPC_7X5_V28 = 152;
+   public static final int UC_CPU_PPC_7400_V10 = 153;
+   public static final int UC_CPU_PPC_7400_V11 = 154;
+   public static final int UC_CPU_PPC_7400_V20 = 155;
+   public static final int UC_CPU_PPC_7400_V21 = 156;
+   public static final int UC_CPU_PPC_7400_V22 = 157;
+   public static final int UC_CPU_PPC_7400_V26 = 158;
+   public static final int UC_CPU_PPC_7400_V27 = 159;
+   public static final int UC_CPU_PPC_7400_V28 = 160;
+   public static final int UC_CPU_PPC_7400_V29 = 161;
+   public static final int UC_CPU_PPC_7410_V10 = 162;
+   public static final int UC_CPU_PPC_7410_V11 = 163;
+   public static final int UC_CPU_PPC_7410_V12 = 164;
+   public static final int UC_CPU_PPC_7410_V13 = 165;
+   public static final int UC_CPU_PPC_7410_V14 = 166;
+   public static final int UC_CPU_PPC_7448_V10 = 167;
+   public static final int UC_CPU_PPC_7448_V11 = 168;
+   public static final int UC_CPU_PPC_7448_V20 = 169;
+   public static final int UC_CPU_PPC_7448_V21 = 170;
+   public static final int UC_CPU_PPC_7450_V10 = 171;
+   public static final int UC_CPU_PPC_7450_V11 = 172;
+   public static final int UC_CPU_PPC_7450_V12 = 173;
+   public static final int UC_CPU_PPC_7450_V20 = 174;
+   public static final int UC_CPU_PPC_7450_V21 = 175;
+   public static final int UC_CPU_PPC_74X1_V23 = 176;
+   public static final int UC_CPU_PPC_74X1_V210 = 177;
+   public static final int UC_CPU_PPC_74X5_V10 = 178;
+   public static final int UC_CPU_PPC_74X5_V21 = 179;
+   public static final int UC_CPU_PPC_74X5_V32 = 180;
+   public static final int UC_CPU_PPC_74X5_V33 = 181;
+   public static final int UC_CPU_PPC_74X5_V34 = 182;
+   public static final int UC_CPU_PPC_74X7_V10 = 183;
+   public static final int UC_CPU_PPC_74X7_V11 = 184;
+   public static final int UC_CPU_PPC_74X7_V12 = 185;
+   public static final int UC_CPU_PPC_74X7A_V10 = 186;
+   public static final int UC_CPU_PPC_74X7A_V11 = 187;
+   public static final int UC_CPU_PPC_74X7A_V12 = 188;
+   public static final int UC_CPU_PPC_IOP480 = 1;
+   public static final int UC_CPU_PPC_X2VP20 = 42;
+   public static final int UC_CPU_PPC_440GRA = 35;
+   public static final int UC_CPU_PPC_440EPX = 38;
+   public static final int UC_CPU_PPC_MPC5200_V10 = 59;
+   public static final int UC_CPU_PPC_MPC5200_V11 = 59;
+   public static final int UC_CPU_PPC_MPC5200_V12 = 59;
+   public static final int UC_CPU_PPC_MPC5200B_V20 = 59;
+   public static final int UC_CPU_PPC_MPC5200B_V21 = 59;
+   public static final int UC_CPU_PPC_MPC834X = 63;
+   public static final int UC_CPU_PPC_MPC837X = 66;
+   public static final int UC_CPU_PPC_E500 = 73;
+   public static final int UC_CPU_PPC_MPC8533_V10 = 72;
+   public static final int UC_CPU_PPC_MPC8533_V11 = 73;
+   public static final int UC_CPU_PPC_MPC8533E_V10 = 72;
+   public static final int UC_CPU_PPC_MPC8533E_V11 = 73;
+   public static final int UC_CPU_PPC_MPC8540_V10 = 67;
+   public static final int UC_CPU_PPC_MPC8540_V20 = 68;
+   public static final int UC_CPU_PPC_MPC8540_V21 = 68;
+   public static final int UC_CPU_PPC_MPC8541_V10 = 68;
+   public static final int UC_CPU_PPC_MPC8541_V11 = 68;
+   public static final int UC_CPU_PPC_MPC8541E_V10 = 68;
+   public static final int UC_CPU_PPC_MPC8541E_V11 = 68;
+   public static final int UC_CPU_PPC_MPC8543_V10 = 69;
+   public static final int UC_CPU_PPC_MPC8543_V11 = 70;
+   public static final int UC_CPU_PPC_MPC8543_V20 = 71;
+   public static final int UC_CPU_PPC_MPC8543_V21 = 72;
+   public static final int UC_CPU_PPC_MPC8543E_V10 = 69;
+   public static final int UC_CPU_PPC_MPC8543E_V11 = 70;
+   public static final int UC_CPU_PPC_MPC8543E_V20 = 71;
+   public static final int UC_CPU_PPC_MPC8543E_V21 = 72;
+   public static final int UC_CPU_PPC_MPC8544_V10 = 72;
+   public static final int UC_CPU_PPC_MPC8544_V11 = 73;
+   public static final int UC_CPU_PPC_MPC8544E_V11 = 73;
+   public static final int UC_CPU_PPC_MPC8544E_V10 = 72;
+   public static final int UC_CPU_PPC_MPC8545_V10 = 69;
+   public static final int UC_CPU_PPC_MPC8545_V20 = 71;
+   public static final int UC_CPU_PPC_MPC8545_V21 = 72;
+   public static final int UC_CPU_PPC_MPC8545E_V10 = 69;
+   public static final int UC_CPU_PPC_MPC8545E_V20 = 71;
+   public static final int UC_CPU_PPC_MPC8545E_V21 = 72;
+   public static final int UC_CPU_PPC_MPC8547E_V10 = 69;
+   public static final int UC_CPU_PPC_MPC8547E_V20 = 71;
+   public static final int UC_CPU_PPC_MPC8547E_V21 = 72;
+   public static final int UC_CPU_PPC_MPC8548_V10 = 69;
+   public static final int UC_CPU_PPC_MPC8548_V11 = 70;
+   public static final int UC_CPU_PPC_MPC8548_V20 = 71;
+   public static final int UC_CPU_PPC_MPC8548_V21 = 72;
+   public static final int UC_CPU_PPC_MPC8548E_V10 = 69;
+   public static final int UC_CPU_PPC_MPC8548E_V11 = 70;
+   public static final int UC_CPU_PPC_MPC8548E_V20 = 71;
+   public static final int UC_CPU_PPC_MPC8548E_V21 = 72;
+   public static final int UC_CPU_PPC_MPC8555_V10 = 69;
+   public static final int UC_CPU_PPC_MPC8555_V11 = 70;
+   public static final int UC_CPU_PPC_MPC8555E_V10 = 69;
+   public static final int UC_CPU_PPC_MPC8555E_V11 = 70;
+   public static final int UC_CPU_PPC_MPC8560_V10 = 69;
+   public static final int UC_CPU_PPC_MPC8560_V20 = 71;
+   public static final int UC_CPU_PPC_MPC8560_V21 = 72;
+   public static final int UC_CPU_PPC_MPC8567 = 73;
+   public static final int UC_CPU_PPC_MPC8567E = 73;
+   public static final int UC_CPU_PPC_MPC8568 = 73;
+   public static final int UC_CPU_PPC_MPC8568E = 73;
+   public static final int UC_CPU_PPC_MPC8572 = 74;
+   public static final int UC_CPU_PPC_MPC8572E = 74;
+   public static final int UC_CPU_PPC_MPC8610 = 78;
+   public static final int UC_CPU_PPC_MPC8641 = 78;
+   public static final int UC_CPU_PPC_MPC8641D = 78;
+
+   public static final int UC_CPU_PPC64_620 = 0;
+   public static final int UC_CPU_PPC64_630 = 1;
+   public static final int UC_CPU_PPC64_631 = 2;
+   public static final int UC_CPU_PPC64_POWER4 = 3;
+   public static final int UC_CPU_PPC64_POWER4P = 4;
+   public static final int UC_CPU_PPC64_POWER5 = 5;
+   public static final int UC_CPU_PPC64_POWER5P_V21 = 6;
+   public static final int UC_CPU_PPC64_POWER6 = 7;
+   public static final int UC_CPU_PPC64_POWER_SERVER_MASK = 8;
+   public static final int UC_CPU_PPC64_POWER7_BASE = 9;
+   public static final int UC_CPU_PPC64_POWER7_V23 = 10;
+   public static final int UC_CPU_PPC64_POWER7P_BASE = 11;
+   public static final int UC_CPU_PPC64_POWER7P_V21 = 12;
+   public static final int UC_CPU_PPC64_POWER8E_BASE = 13;
+   public static final int UC_CPU_PPC64_POWER8E_V21 = 14;
+   public static final int UC_CPU_PPC64_POWER8_BASE = 15;
+   public static final int UC_CPU_PPC64_POWER8_V20 = 16;
+   public static final int UC_CPU_PPC64_POWER8NVL_BASE = 17;
+   public static final int UC_CPU_PPC64_POWER8NVL_V10 = 18;
+   public static final int UC_CPU_PPC64_POWER9_BASE = 19;
+   public static final int UC_CPU_PPC64_POWER9_DD1 = 20;
+   public static final int UC_CPU_PPC64_POWER9_DD20 = 21;
+   public static final int UC_CPU_PPC64_POWER10_BASE = 22;
+   public static final int UC_CPU_PPC64_POWER10_DD1 = 23;
+   public static final int UC_CPU_PPC64_970_V22 = 24;
+   public static final int UC_CPU_PPC64_970FX_V10 = 25;
+   public static final int UC_CPU_PPC64_970FX_V20 = 26;
+   public static final int UC_CPU_PPC64_970FX_V21 = 27;
+   public static final int UC_CPU_PPC64_970FX_V30 = 28;
+   public static final int UC_CPU_PPC64_970FX_V31 = 29;
+   public static final int UC_CPU_PPC64_970MP_V10 = 30;
+   public static final int UC_CPU_PPC64_970MP_V11 = 31;
+   public static final int UC_CPU_PPC64_CELL_V10 = 32;
+   public static final int UC_CPU_PPC64_CELL_V20 = 33;
+   public static final int UC_CPU_PPC64_CELL_V30 = 34;
+   public static final int UC_CPU_PPC64_CELL_V31 = 35;
+   public static final int UC_CPU_PPC64_RS64 = 36;
+   public static final int UC_CPU_PPC64_RS64II = 37;
+   public static final int UC_CPU_PPC64_RS64III = 38;
+   public static final int UC_CPU_PPC64_RS64IV = 39;
+   public static final int UC_CPU_PPC64_CELL_V32 = 35;
+   public static final int UC_CPU_PPC64_CELL = 35;
+
 // PPC registers
 
    public static final int UC_PPC_REG_INVALID = 0;

bindings/java/unicorn/RiscvConst.java

@@ -4,6 +4,16 @@ package unicorn;
 
 public interface RiscvConst {
 
+   public static final int UC_CPU_RISCV32_ANY = 0;
+   public static final int UC_CPU_RISCV32_BASE32 = 1;
+   public static final int UC_CPU_RISCV32_SIFIVE_E31 = 2;
+   public static final int UC_CPU_RISCV32_SIFIVE_U34 = 3;
+
+   public static final int UC_CPU_RISCV64_ANY = 0;
+   public static final int UC_CPU_RISCV64_BASE64 = 1;
+   public static final int UC_CPU_RISCV64_SIFIVE_E51 = 2;
+   public static final int UC_CPU_RISCV64_SIFIVE_U54 = 3;
+
 // RISCV registers
 
    public static final int UC_RISCV_REG_INVALID = 0;

bindings/java/unicorn/SparcConst.java

@@ -4,6 +4,38 @@ package unicorn;
 
 public interface SparcConst {
 
+   public static final int UC_CPU_SPARC_FUJITSU_MB86904 = 0;
+   public static final int UC_CPU_SPARC_FUJITSU_MB86907 = 1;
+   public static final int UC_CPU_SPARC_TI_MICROSPARC_I = 2;
+   public static final int UC_CPU_SPARC_TI_MICROSPARC_II = 3;
+   public static final int UC_CPU_SPARC_TI_MICROSPARC_IIEP = 4;
+   public static final int UC_CPU_SPARC_TI_SUPERSPARC_40 = 5;
+   public static final int UC_CPU_SPARC_TI_SUPERSPARC_50 = 6;
+   public static final int UC_CPU_SPARC_TI_SUPERSPARC_51 = 7;
+   public static final int UC_CPU_SPARC_TI_SUPERSPARC_60 = 8;
+   public static final int UC_CPU_SPARC_TI_SUPERSPARC_61 = 9;
+   public static final int UC_CPU_SPARC_TI_SUPERSPARC_II = 10;
+   public static final int UC_CPU_SPARC_LEON2 = 11;
+   public static final int UC_CPU_SPARC_LEON3 = 12;
+
+   public static final int UC_CPU_SPARC64_FUJITSU = 0;
+   public static final int UC_CPU_SPARC64_FUJITSU_III = 1;
+   public static final int UC_CPU_SPARC64_FUJITSU_IV = 2;
+   public static final int UC_CPU_SPARC64_FUJITSU_V = 3;
+   public static final int UC_CPU_SPARC64_TI_ULTRASPARC_I = 4;
+   public static final int UC_CPU_SPARC64_TI_ULTRASPARC_II = 5;
+   public static final int UC_CPU_SPARC64_TI_ULTRASPARC_III = 6;
+   public static final int UC_CPU_SPARC64_TI_ULTRASPARC_IIE = 7;
+   public static final int UC_CPU_SPARC64_SUN_ULTRASPARC_III = 8;
+   public static final int UC_CPU_SPARC64_SUN_ULTRASPARC_III_CU = 9;
+   public static final int UC_CPU_SPARC64_SUN_ULTRASPARC_IIII = 10;
+   public static final int UC_CPU_SPARC64_SUN_ULTRASPARC_IV = 11;
+   public static final int UC_CPU_SPARC64_SUN_ULTRASPARC_IV_PLUS = 12;
+   public static final int UC_CPU_SPARC64_SUN_ULTRASPARC_IIII_PLUS = 13;
+   public static final int UC_CPU_SPARC64_SUN_ULTRASPARC_T1 = 14;
+   public static final int UC_CPU_SPARC64_SUN_ULTRASPARC_T2 = 15;
+   public static final int UC_CPU_SPARC64_NEC_ULTRASPARC_I = 16;
+
 // SPARC registers
 
    public static final int UC_SPARC_REG_INVALID = 0;

bindings/java/unicorn/UnicornConst.java

@@ -109,6 +109,22 @@ public interface UnicornConst {
    public static final int UC_QUERY_ARCH = 3;
    public static final int UC_QUERY_TIMEOUT = 4;
 
+   public static final int UC_CTL_IO_NONE = 0;
+   public static final int UC_CTL_IO_WRITE = 1;
+   public static final int UC_CTL_IO_READ = 2;
+   public static final int UC_CTL_IO_READ_WRITE = 3;
+
+   public static final int UC_CTL_UC_MODE = 0;
+   public static final int UC_CTL_UC_PAGE_SIZE = 1;
+   public static final int UC_CTL_UC_ARCH = 2;
+   public static final int UC_CTL_UC_TIMEOUT = 3;
+   public static final int UC_CTL_UC_EXITS_CNT = 4;
+   public static final int UC_CTL_UC_EXITS = 5;
+   public static final int UC_CTL_CPU_MODEL = 6;
+   public static final int UC_CTL_TB_EDGE = 7;
+   public static final int UC_CTL_TB_REQUEST_CACHE = 8;
+   public static final int UC_CTL_TB_REMOVE_CACHE = 9;
+
    public static final int UC_PROT_NONE = 0;
    public static final int UC_PROT_READ = 1;
    public static final int UC_PROT_WRITE = 2;

bindings/java/unicorn/X86Const.java

@@ -4,6 +4,45 @@ package unicorn;
 
 public interface X86Const {
 
+   public static final int UC_CPU_X86_QEMU64 = 0;
+   public static final int UC_CPU_X86_PHENOM = 1;
+   public static final int UC_CPU_X86_CORE2DUO = 2;
+   public static final int UC_CPU_X86_KVM64 = 3;
+   public static final int UC_CPU_X86_QEMU32 = 4;
+   public static final int UC_CPU_X86_KVM32 = 5;
+   public static final int UC_CPU_X86_COREDUO = 6;
+   public static final int UC_CPU_X86_486 = 7;
+   public static final int UC_CPU_X86_PENTIUM = 8;
+   public static final int UC_CPU_X86_PENTIUM2 = 9;
+   public static final int UC_CPU_X86_PENTIUM3 = 10;
+   public static final int UC_CPU_X86_ATHLON = 11;
+   public static final int UC_CPU_X86_N270 = 12;
+   public static final int UC_CPU_X86_CONROE = 13;
+   public static final int UC_CPU_X86_PENRYN = 14;
+   public static final int UC_CPU_X86_NEHALEM = 15;
+   public static final int UC_CPU_X86_WESTMERE = 16;
+   public static final int UC_CPU_X86_SANDYBRIDGE = 17;
+   public static final int UC_CPU_X86_IVYBRIDGE = 18;
+   public static final int UC_CPU_X86_HASWELL = 19;
+   public static final int UC_CPU_X86_BROADWELL = 20;
+   public static final int UC_CPU_X86_SKYLAKE_CLIENT = 21;
+   public static final int UC_CPU_X86_SKYLAKE_SERVER = 22;
+   public static final int UC_CPU_X86_CASCADELAKE_SERVER = 23;
+   public static final int UC_CPU_X86_COOPERLAKE = 24;
+   public static final int UC_CPU_X86_ICELAKE_CLIENT = 25;
+   public static final int UC_CPU_X86_ICELAKE_SERVER = 26;
+   public static final int UC_CPU_X86_DENVERTON = 27;
+   public static final int UC_CPU_X86_SNOWRIDGE = 28;
+   public static final int UC_CPU_X86_KNIGHTSMILL = 29;
+   public static final int UC_CPU_X86_OPTERON_G1 = 30;
+   public static final int UC_CPU_X86_OPTERON_G2 = 31;
+   public static final int UC_CPU_X86_OPTERON_G3 = 32;
+   public static final int UC_CPU_X86_OPTERON_G4 = 33;
+   public static final int UC_CPU_X86_OPTERON_G5 = 34;
+   public static final int UC_CPU_X86_EPYC = 35;
+   public static final int UC_CPU_X86_DHYANA = 36;
+   public static final int UC_CPU_X86_EPYC_ROME = 37;
+
 // X86 registers
 
    public static final int UC_X86_REG_INVALID = 0;

bindings/pascal/unicorn/Arm64Const.pas

@@ -5,6 +5,11 @@ unit Arm64Const;
 interface
 
 const
+  UC_CPU_AARCH64_A57 = 0;
+  UC_CPU_AARCH64_A53 = 1;
+  UC_CPU_AARCH64_A72 = 2;
+  UC_CPU_AARCH64_MAX = 3;
+
 // ARM64 registers
 
   UC_ARM64_REG_INVALID = 0;

bindings/pascal/unicorn/ArmConst.pas

@@ -5,6 +5,40 @@ unit ArmConst;
 interface
 
 const
+  UC_CPU_ARM_926 = 0;
+  UC_CPU_ARM_946 = 1;
+  UC_CPU_ARM_1026 = 2;
+  UC_CPU_ARM_1136_R2 = 3;
+  UC_CPU_ARM_1136 = 4;
+  UC_CPU_ARM_1176 = 5;
+  UC_CPU_ARM_11MPCORE = 6;
+  UC_CPU_ARM_CORTEX_M0 = 7;
+  UC_CPU_ARM_CORTEX_M3 = 8;
+  UC_CPU_ARM_CORTEX_M4 = 9;
+  UC_CPU_ARM_CORTEX_M7 = 10;
+  UC_CPU_ARM_CORTEX_M33 = 11;
+  UC_CPU_ARM_CORTEX_R5 = 12;
+  UC_CPU_ARM_CORTEX_R5F = 13;
+  UC_CPU_ARM_CORTEX_A8 = 14;
+  UC_CPU_ARM_CORTEX_A9 = 15;
+  UC_CPU_ARM_CORTEX_A7 = 16;
+  UC_CPU_ARM_CORTEX_A15 = 17;
+  UC_CPU_ARM_TI925T = 18;
+  UC_CPU_ARM_SA1100 = 19;
+  UC_CPU_ARM_SA1110 = 20;
+  UC_CPU_ARM_PXA250 = 21;
+  UC_CPU_ARM_PXA255 = 22;
+  UC_CPU_ARM_PXA260 = 23;
+  UC_CPU_ARM_PXA261 = 24;
+  UC_CPU_ARM_PXA262 = 25;
+  UC_CPU_ARM_PXA270A0 = 26;
+  UC_CPU_ARM_PXA270A1 = 27;
+  UC_CPU_ARM_PXA270B0 = 28;
+  UC_CPU_ARM_PXA270B1 = 29;
+  UC_CPU_ARM_PXA270C0 = 30;
+  UC_CPU_ARM_PXA270C5 = 31;
+  UC_CPU_ARM_MAX = 32;
+
 // ARM registers
 
   UC_ARM_REG_INVALID = 0;

bindings/pascal/unicorn/M68kConst.pas

@@ -5,6 +5,16 @@ unit M68kConst;
 interface
 
 const
+  UC_CPU_M5206_CPU = 0;
+  UC_CPU_M68000_CPU = 1;
+  UC_CPU_M68020_CPU = 2;
+  UC_CPU_M68030_CPU = 3;
+  UC_CPU_M68040_CPU = 4;
+  UC_CPU_M68060_CPU = 5;
+  UC_CPU_M5208_CPU = 6;
+  UC_CPU_CFV4E_CPU = 7;
+  UC_CPU_ANY_CPU = 8;
+
 // M68K registers
 
   UC_M68K_REG_INVALID = 0;

bindings/pascal/unicorn/MipsConst.pas

@@ -5,6 +5,36 @@ unit MipsConst;
 interface
 
 const
+  UC_CPU_MIPS_4KC = 0;
+  UC_CPU_MIPS_4KM = 1;
+  UC_CPU_MIPS_4KECR1 = 2;
+  UC_CPU_MIPS_4KEMR1 = 3;
+  UC_CPU_MIPS_4KEC = 4;
+  UC_CPU_MIPS_4KEM = 5;
+  UC_CPU_MIPS_24KC = 6;
+  UC_CPU_MIPS_24KEC = 7;
+  UC_CPU_MIPS_24KF = 8;
+  UC_CPU_MIPS_34KF = 9;
+  UC_CPU_MIPS_74KF = 10;
+  UC_CPU_MIPS_M14K = 11;
+  UC_CPU_MIPS_M14KC = 12;
+  UC_CPU_MIPS_P5600 = 13;
+  UC_CPU_MIPS_MIPS32R6_GENERIC = 14;
+  UC_CPU_MIPS_I7200 = 15;
+  UC_CPU_MIPS_R4000 = 16;
+  UC_CPU_MIPS_VR5432 = 17;
+  UC_CPU_MIPS_5KC = 18;
+  UC_CPU_MIPS_5KF = 19;
+  UC_CPU_MIPS_20KC = 20;
+  UC_CPU_MIPS_MIPS64R2_GENERIC = 21;
+  UC_CPU_MIPS_5KEC = 22;
+  UC_CPU_MIPS_5KEF = 23;
+  UC_CPU_MIPS_I6400 = 24;
+  UC_CPU_MIPS_I6500 = 25;
+  UC_CPU_MIPS_LOONGSON_2E = 26;
+  UC_CPU_MIPS_LOONGSON_2F = 27;
+  UC_CPU_MIPS_MIPS64DSPR2 = 28;
+
 // MIPS registers
 
   UC_MIPS_REG_INVALID = 0;

bindings/pascal/unicorn/PpcConst.pas

@@ -5,6 +5,307 @@ unit PpcConst;
 interface
 
 const
+  UC_CPU_PPC_401A1 = 0;
+  UC_CPU_PPC_401B2 = 1;
+  UC_CPU_PPC_401C2 = 2;
+  UC_CPU_PPC_401D2 = 3;
+  UC_CPU_PPC_401E2 = 4;
+  UC_CPU_PPC_401F2 = 5;
+  UC_CPU_PPC_401G2 = 6;
+  UC_CPU_PPC_COBRA = 7;
+  UC_CPU_PPC_403GA = 8;
+  UC_CPU_PPC_403GB = 9;
+  UC_CPU_PPC_403GC = 10;
+  UC_CPU_PPC_403GCX = 11;
+  UC_CPU_PPC_405D2 = 12;
+  UC_CPU_PPC_405D4 = 13;
+  UC_CPU_PPC_405CRA = 14;
+  UC_CPU_PPC_405CRB = 15;
+  UC_CPU_PPC_405CRC = 16;
+  UC_CPU_PPC_405EP = 17;
+  UC_CPU_PPC_405EZ = 18;
+  UC_CPU_PPC_405GPA = 19;
+  UC_CPU_PPC_405GPB = 20;
+  UC_CPU_PPC_405GPC = 21;
+  UC_CPU_PPC_405GPD = 22;
+  UC_CPU_PPC_405GPR = 23;
+  UC_CPU_PPC_405LP = 24;
+  UC_CPU_PPC_NPE405H = 25;
+  UC_CPU_PPC_NPE405H2 = 26;
+  UC_CPU_PPC_NPE405L = 27;
+  UC_CPU_PPC_NPE4GS3 = 28;
+  UC_CPU_PPC_STB03 = 29;
+  UC_CPU_PPC_STB04 = 30;
+  UC_CPU_PPC_STB25 = 31;
+  UC_CPU_PPC_X2VP4 = 32;
+  UC_CPU_PPC_440_XILINX = 33;
+  UC_CPU_PPC_440EPA = 34;
+  UC_CPU_PPC_440EPB = 35;
+  UC_CPU_PPC_440GPB = 36;
+  UC_CPU_PPC_440GPC = 37;
+  UC_CPU_PPC_440GRX = 38;
+  UC_CPU_PPC_440GXA = 39;
+  UC_CPU_PPC_440GXB = 40;
+  UC_CPU_PPC_440GXC = 41;
+  UC_CPU_PPC_440GXF = 42;
+  UC_CPU_PPC_440SP = 43;
+  UC_CPU_PPC_440SP2 = 44;
+  UC_CPU_PPC_440SPE = 45;
+  UC_CPU_PPC_460EXB = 46;
+  UC_CPU_PPC_MPC5XX = 47;
+  UC_CPU_PPC_MPC8XX = 48;
+  UC_CPU_PPC_G2 = 49;
+  UC_CPU_PPC_G2H4 = 50;
+  UC_CPU_PPC_G2GP = 51;
+  UC_CPU_PPC_G2LS = 52;
+  UC_CPU_PPC_MPC603 = 53;
+  UC_CPU_PPC_G2_HIP3 = 54;
+  UC_CPU_PPC_G2_HIP4 = 55;
+  UC_CPU_PPC_G2LE = 56;
+  UC_CPU_PPC_G2LEGP = 57;
+  UC_CPU_PPC_G2LELS = 58;
+  UC_CPU_PPC_G2LEGP1 = 59;
+  UC_CPU_PPC_G2LEGP3 = 60;
+  UC_CPU_PPC_E200Z5 = 61;
+  UC_CPU_PPC_E200Z6 = 62;
+  UC_CPU_PPC_E300C1 = 63;
+  UC_CPU_PPC_E300C2 = 64;
+  UC_CPU_PPC_E300C3 = 65;
+  UC_CPU_PPC_E300C4 = 66;
+  UC_CPU_PPC_E500V1_V10 = 67;
+  UC_CPU_PPC_E500V1_V20 = 68;
+  UC_CPU_PPC_E500V2_V10 = 69;
+  UC_CPU_PPC_E500V2_V11 = 70;
+  UC_CPU_PPC_E500V2_V20 = 71;
+  UC_CPU_PPC_E500V2_V21 = 72;
+  UC_CPU_PPC_E500V2_V22 = 73;
+  UC_CPU_PPC_E500V2_V30 = 74;
+  UC_CPU_PPC_E500MC = 75;
+  UC_CPU_PPC_E5500 = 76;
+  UC_CPU_PPC_E6500 = 77;
+  UC_CPU_PPC_E600 = 78;
+  UC_CPU_PPC_601_V0 = 79;
+  UC_CPU_PPC_601_V1 = 80;
+  UC_CPU_PPC_601_V2 = 81;
+  UC_CPU_PPC_602 = 82;
+  UC_CPU_PPC_603 = 83;
+  UC_CPU_PPC_603E_V11 = 84;
+  UC_CPU_PPC_603E_V12 = 85;
+  UC_CPU_PPC_603E_V13 = 86;
+  UC_CPU_PPC_603E_V14 = 87;
+  UC_CPU_PPC_603E_V22 = 88;
+  UC_CPU_PPC_603E_V3 = 89;
+  UC_CPU_PPC_603E_V4 = 90;
+  UC_CPU_PPC_603E_V41 = 91;
+  UC_CPU_PPC_603E7T = 92;
+  UC_CPU_PPC_603E7V = 93;
+  UC_CPU_PPC_603E7V1 = 94;
+  UC_CPU_PPC_603E7V2 = 95;
+  UC_CPU_PPC_603E7 = 96;
+  UC_CPU_PPC_603P = 97;
+  UC_CPU_PPC_604 = 98;
+  UC_CPU_PPC_604E_V10 = 99;
+  UC_CPU_PPC_604E_V22 = 100;
+  UC_CPU_PPC_604E_V24 = 101;
+  UC_CPU_PPC_604R = 102;
+  UC_CPU_PPC_7X0_V10 = 103;
+  UC_CPU_PPC_7X0_V20 = 104;
+  UC_CPU_PPC_7X0_V21 = 105;
+  UC_CPU_PPC_7X0_V22 = 106;
+  UC_CPU_PPC_7X0_V30 = 107;
+  UC_CPU_PPC_7X0_V31 = 108;
+  UC_CPU_PPC_740E = 109;
+  UC_CPU_PPC_750E = 110;
+  UC_CPU_PPC_7X0P = 111;
+  UC_CPU_PPC_750CL_V10 = 112;
+  UC_CPU_PPC_750CL_V20 = 113;
+  UC_CPU_PPC_750CX_V10 = 114;
+  UC_CPU_PPC_750CX_V20 = 115;
+  UC_CPU_PPC_750CX_V21 = 116;
+  UC_CPU_PPC_750CX_V22 = 117;
+  UC_CPU_PPC_750CXE_V21 = 118;
+  UC_CPU_PPC_750CXE_V22 = 119;
+  UC_CPU_PPC_750CXE_V23 = 120;
+  UC_CPU_PPC_750CXE_V24 = 121;
+  UC_CPU_PPC_750CXE_V24B = 122;
+  UC_CPU_PPC_750CXE_V30 = 123;
+  UC_CPU_PPC_750CXE_V31 = 124;
+  UC_CPU_PPC_750CXE_V31B = 125;
+  UC_CPU_PPC_750CXR = 126;
+  UC_CPU_PPC_750FL = 127;
+  UC_CPU_PPC_750FX_V10 = 128;
+  UC_CPU_PPC_750FX_V20 = 129;
+  UC_CPU_PPC_750FX_V21 = 130;
+  UC_CPU_PPC_750FX_V22 = 131;
+  UC_CPU_PPC_750FX_V23 = 132;
+  UC_CPU_PPC_750GL = 133;
+  UC_CPU_PPC_750GX_V10 = 134;
+  UC_CPU_PPC_750GX_V11 = 135;
+  UC_CPU_PPC_750GX_V12 = 136;
+  UC_CPU_PPC_750L_V20 = 137;
+  UC_CPU_PPC_750L_V21 = 138;
+  UC_CPU_PPC_750L_V22 = 139;
+  UC_CPU_PPC_750L_V30 = 140;
+  UC_CPU_PPC_750L_V32 = 141;
+  UC_CPU_PPC_7X5_V10 = 142;
+  UC_CPU_PPC_7X5_V11 = 143;
+  UC_CPU_PPC_7X5_V20 = 144;
+  UC_CPU_PPC_7X5_V21 = 145;
+  UC_CPU_PPC_7X5_V22 = 146;
+  UC_CPU_PPC_7X5_V23 = 147;
+  UC_CPU_PPC_7X5_V24 = 148;
+  UC_CPU_PPC_7X5_V25 = 149;
+  UC_CPU_PPC_7X5_V26 = 150;
+  UC_CPU_PPC_7X5_V27 = 151;
+  UC_CPU_PPC_7X5_V28 = 152;
+  UC_CPU_PPC_7400_V10 = 153;
+  UC_CPU_PPC_7400_V11 = 154;
+  UC_CPU_PPC_7400_V20 = 155;
+  UC_CPU_PPC_7400_V21 = 156;
+  UC_CPU_PPC_7400_V22 = 157;
+  UC_CPU_PPC_7400_V26 = 158;
+  UC_CPU_PPC_7400_V27 = 159;
+  UC_CPU_PPC_7400_V28 = 160;
+  UC_CPU_PPC_7400_V29 = 161;
+  UC_CPU_PPC_7410_V10 = 162;
+  UC_CPU_PPC_7410_V11 = 163;
+  UC_CPU_PPC_7410_V12 = 164;
+  UC_CPU_PPC_7410_V13 = 165;
+  UC_CPU_PPC_7410_V14 = 166;
+  UC_CPU_PPC_7448_V10 = 167;
+  UC_CPU_PPC_7448_V11 = 168;
+  UC_CPU_PPC_7448_V20 = 169;
+  UC_CPU_PPC_7448_V21 = 170;
+  UC_CPU_PPC_7450_V10 = 171;
+  UC_CPU_PPC_7450_V11 = 172;
+  UC_CPU_PPC_7450_V12 = 173;
+  UC_CPU_PPC_7450_V20 = 174;
+  UC_CPU_PPC_7450_V21 = 175;
+  UC_CPU_PPC_74X1_V23 = 176;
+  UC_CPU_PPC_74X1_V210 = 177;
+  UC_CPU_PPC_74X5_V10 = 178;
+  UC_CPU_PPC_74X5_V21 = 179;
+  UC_CPU_PPC_74X5_V32 = 180;
+  UC_CPU_PPC_74X5_V33 = 181;
+  UC_CPU_PPC_74X5_V34 = 182;
+  UC_CPU_PPC_74X7_V10 = 183;
+  UC_CPU_PPC_74X7_V11 = 184;
+  UC_CPU_PPC_74X7_V12 = 185;
+  UC_CPU_PPC_74X7A_V10 = 186;
+  UC_CPU_PPC_74X7A_V11 = 187;
+  UC_CPU_PPC_74X7A_V12 = 188;
+  UC_CPU_PPC_IOP480 = 1;
+  UC_CPU_PPC_X2VP20 = 42;
+  UC_CPU_PPC_440GRA = 35;
+  UC_CPU_PPC_440EPX = 38;
+  UC_CPU_PPC_MPC5200_V10 = 59;
+  UC_CPU_PPC_MPC5200_V11 = 59;
+  UC_CPU_PPC_MPC5200_V12 = 59;
+  UC_CPU_PPC_MPC5200B_V20 = 59;
+  UC_CPU_PPC_MPC5200B_V21 = 59;
+  UC_CPU_PPC_MPC834X = 63;
+  UC_CPU_PPC_MPC837X = 66;
+  UC_CPU_PPC_E500 = 73;
+  UC_CPU_PPC_MPC8533_V10 = 72;
+  UC_CPU_PPC_MPC8533_V11 = 73;
+  UC_CPU_PPC_MPC8533E_V10 = 72;
+  UC_CPU_PPC_MPC8533E_V11 = 73;
+  UC_CPU_PPC_MPC8540_V10 = 67;
+  UC_CPU_PPC_MPC8540_V20 = 68;
+  UC_CPU_PPC_MPC8540_V21 = 68;
+  UC_CPU_PPC_MPC8541_V10 = 68;
+  UC_CPU_PPC_MPC8541_V11 = 68;
+  UC_CPU_PPC_MPC8541E_V10 = 68;
+  UC_CPU_PPC_MPC8541E_V11 = 68;
+  UC_CPU_PPC_MPC8543_V10 = 69;
+  UC_CPU_PPC_MPC8543_V11 = 70;
+  UC_CPU_PPC_MPC8543_V20 = 71;
+  UC_CPU_PPC_MPC8543_V21 = 72;
+  UC_CPU_PPC_MPC8543E_V10 = 69;
+  UC_CPU_PPC_MPC8543E_V11 = 70;
+  UC_CPU_PPC_MPC8543E_V20 = 71;
+  UC_CPU_PPC_MPC8543E_V21 = 72;
+  UC_CPU_PPC_MPC8544_V10 = 72;
+  UC_CPU_PPC_MPC8544_V11 = 73;
+  UC_CPU_PPC_MPC8544E_V11 = 73;
+  UC_CPU_PPC_MPC8544E_V10 = 72;
+  UC_CPU_PPC_MPC8545_V10 = 69;
+  UC_CPU_PPC_MPC8545_V20 = 71;
+  UC_CPU_PPC_MPC8545_V21 = 72;
+  UC_CPU_PPC_MPC8545E_V10 = 69;
+  UC_CPU_PPC_MPC8545E_V20 = 71;
+  UC_CPU_PPC_MPC8545E_V21 = 72;
+  UC_CPU_PPC_MPC8547E_V10 = 69;
+  UC_CPU_PPC_MPC8547E_V20 = 71;
+  UC_CPU_PPC_MPC8547E_V21 = 72;
+  UC_CPU_PPC_MPC8548_V10 = 69;
+  UC_CPU_PPC_MPC8548_V11 = 70;
+  UC_CPU_PPC_MPC8548_V20 = 71;
+  UC_CPU_PPC_MPC8548_V21 = 72;
+  UC_CPU_PPC_MPC8548E_V10 = 69;
+  UC_CPU_PPC_MPC8548E_V11 = 70;
+  UC_CPU_PPC_MPC8548E_V20 = 71;
+  UC_CPU_PPC_MPC8548E_V21 = 72;
+  UC_CPU_PPC_MPC8555_V10 = 69;
+  UC_CPU_PPC_MPC8555_V11 = 70;
+  UC_CPU_PPC_MPC8555E_V10 = 69;
+  UC_CPU_PPC_MPC8555E_V11 = 70;
+  UC_CPU_PPC_MPC8560_V10 = 69;
+  UC_CPU_PPC_MPC8560_V20 = 71;
+  UC_CPU_PPC_MPC8560_V21 = 72;
+  UC_CPU_PPC_MPC8567 = 73;
+  UC_CPU_PPC_MPC8567E = 73;
+  UC_CPU_PPC_MPC8568 = 73;
+  UC_CPU_PPC_MPC8568E = 73;
+  UC_CPU_PPC_MPC8572 = 74;
+  UC_CPU_PPC_MPC8572E = 74;
+  UC_CPU_PPC_MPC8610 = 78;
+  UC_CPU_PPC_MPC8641 = 78;
+  UC_CPU_PPC_MPC8641D = 78;
+
+  UC_CPU_PPC64_620 = 0;
+  UC_CPU_PPC64_630 = 1;
+  UC_CPU_PPC64_631 = 2;
+  UC_CPU_PPC64_POWER4 = 3;
+  UC_CPU_PPC64_POWER4P = 4;
+  UC_CPU_PPC64_POWER5 = 5;
+  UC_CPU_PPC64_POWER5P_V21 = 6;
+  UC_CPU_PPC64_POWER6 = 7;
+  UC_CPU_PPC64_POWER_SERVER_MASK = 8;
+  UC_CPU_PPC64_POWER7_BASE = 9;
+  UC_CPU_PPC64_POWER7_V23 = 10;
+  UC_CPU_PPC64_POWER7P_BASE = 11;
+  UC_CPU_PPC64_POWER7P_V21 = 12;
+  UC_CPU_PPC64_POWER8E_BASE = 13;
+  UC_CPU_PPC64_POWER8E_V21 = 14;
+  UC_CPU_PPC64_POWER8_BASE = 15;
+  UC_CPU_PPC64_POWER8_V20 = 16;
+  UC_CPU_PPC64_POWER8NVL_BASE = 17;
+  UC_CPU_PPC64_POWER8NVL_V10 = 18;
+  UC_CPU_PPC64_POWER9_BASE = 19;
+  UC_CPU_PPC64_POWER9_DD1 = 20;
+  UC_CPU_PPC64_POWER9_DD20 = 21;
+  UC_CPU_PPC64_POWER10_BASE = 22;
+  UC_CPU_PPC64_POWER10_DD1 = 23;
+  UC_CPU_PPC64_970_V22 = 24;
+  UC_CPU_PPC64_970FX_V10 = 25;
+  UC_CPU_PPC64_970FX_V20 = 26;
+  UC_CPU_PPC64_970FX_V21 = 27;
+  UC_CPU_PPC64_970FX_V30 = 28;
+  UC_CPU_PPC64_970FX_V31 = 29;
+  UC_CPU_PPC64_970MP_V10 = 30;
+  UC_CPU_PPC64_970MP_V11 = 31;
+  UC_CPU_PPC64_CELL_V10 = 32;
+  UC_CPU_PPC64_CELL_V20 = 33;
+  UC_CPU_PPC64_CELL_V30 = 34;
+  UC_CPU_PPC64_CELL_V31 = 35;
+  UC_CPU_PPC64_RS64 = 36;
+  UC_CPU_PPC64_RS64II = 37;
+  UC_CPU_PPC64_RS64III = 38;
+  UC_CPU_PPC64_RS64IV = 39;
+  UC_CPU_PPC64_CELL_V32 = 35;
+  UC_CPU_PPC64_CELL = 35;
+
 // PPC registers
 
   UC_PPC_REG_INVALID = 0;

bindings/pascal/unicorn/RiscvConst.pas

@@ -5,6 +5,16 @@ unit RiscvConst;
 interface
 
 const
+  UC_CPU_RISCV32_ANY = 0;
+  UC_CPU_RISCV32_BASE32 = 1;
+  UC_CPU_RISCV32_SIFIVE_E31 = 2;
+  UC_CPU_RISCV32_SIFIVE_U34 = 3;
+
+  UC_CPU_RISCV64_ANY = 0;
+  UC_CPU_RISCV64_BASE64 = 1;
+  UC_CPU_RISCV64_SIFIVE_E51 = 2;
+  UC_CPU_RISCV64_SIFIVE_U54 = 3;
+
 // RISCV registers
 
   UC_RISCV_REG_INVALID = 0;

bindings/pascal/unicorn/SparcConst.pas

@@ -5,6 +5,38 @@ unit SparcConst;
 interface
 
 const
+  UC_CPU_SPARC_FUJITSU_MB86904 = 0;
+  UC_CPU_SPARC_FUJITSU_MB86907 = 1;
+  UC_CPU_SPARC_TI_MICROSPARC_I = 2;
+  UC_CPU_SPARC_TI_MICROSPARC_II = 3;
+  UC_CPU_SPARC_TI_MICROSPARC_IIEP = 4;
+  UC_CPU_SPARC_TI_SUPERSPARC_40 = 5;
+  UC_CPU_SPARC_TI_SUPERSPARC_50 = 6;
+  UC_CPU_SPARC_TI_SUPERSPARC_51 = 7;
+  UC_CPU_SPARC_TI_SUPERSPARC_60 = 8;
+  UC_CPU_SPARC_TI_SUPERSPARC_61 = 9;
+  UC_CPU_SPARC_TI_SUPERSPARC_II = 10;
+  UC_CPU_SPARC_LEON2 = 11;
+  UC_CPU_SPARC_LEON3 = 12;
+
+  UC_CPU_SPARC64_FUJITSU = 0;
+  UC_CPU_SPARC64_FUJITSU_III = 1;
+  UC_CPU_SPARC64_FUJITSU_IV = 2;
+  UC_CPU_SPARC64_FUJITSU_V = 3;
+  UC_CPU_SPARC64_TI_ULTRASPARC_I = 4;
+  UC_CPU_SPARC64_TI_ULTRASPARC_II = 5;
+  UC_CPU_SPARC64_TI_ULTRASPARC_III = 6;
+  UC_CPU_SPARC64_TI_ULTRASPARC_IIE = 7;
+  UC_CPU_SPARC64_SUN_ULTRASPARC_III = 8;
+  UC_CPU_SPARC64_SUN_ULTRASPARC_III_CU = 9;
+  UC_CPU_SPARC64_SUN_ULTRASPARC_IIII = 10;
+  UC_CPU_SPARC64_SUN_ULTRASPARC_IV = 11;
+  UC_CPU_SPARC64_SUN_ULTRASPARC_IV_PLUS = 12;
+  UC_CPU_SPARC64_SUN_ULTRASPARC_IIII_PLUS = 13;
+  UC_CPU_SPARC64_SUN_ULTRASPARC_T1 = 14;
+  UC_CPU_SPARC64_SUN_ULTRASPARC_T2 = 15;
+  UC_CPU_SPARC64_NEC_ULTRASPARC_I = 16;
+
 // SPARC registers
 
   UC_SPARC_REG_INVALID = 0;

bindings/pascal/unicorn/UnicornConst.pas

@@ -110,6 +110,22 @@ const  UC_API_MAJOR = 2;
   UC_QUERY_ARCH = 3;
   UC_QUERY_TIMEOUT = 4;
 
+  UC_CTL_IO_NONE = 0;
+  UC_CTL_IO_WRITE = 1;
+  UC_CTL_IO_READ = 2;
+  UC_CTL_IO_READ_WRITE = 3;
+
+  UC_CTL_UC_MODE = 0;
+  UC_CTL_UC_PAGE_SIZE = 1;
+  UC_CTL_UC_ARCH = 2;
+  UC_CTL_UC_TIMEOUT = 3;
+  UC_CTL_UC_EXITS_CNT = 4;
+  UC_CTL_UC_EXITS = 5;
+  UC_CTL_CPU_MODEL = 6;
+  UC_CTL_TB_EDGE = 7;
+  UC_CTL_TB_REQUEST_CACHE = 8;
+  UC_CTL_TB_REMOVE_CACHE = 9;
+
   UC_PROT_NONE = 0;
   UC_PROT_READ = 1;
   UC_PROT_WRITE = 2;

bindings/pascal/unicorn/X86Const.pas

@@ -5,6 +5,45 @@ unit X86Const;
 interface
 
 const
+  UC_CPU_X86_QEMU64 = 0;
+  UC_CPU_X86_PHENOM = 1;
+  UC_CPU_X86_CORE2DUO = 2;
+  UC_CPU_X86_KVM64 = 3;
+  UC_CPU_X86_QEMU32 = 4;
+  UC_CPU_X86_KVM32 = 5;
+  UC_CPU_X86_COREDUO = 6;
+  UC_CPU_X86_486 = 7;
+  UC_CPU_X86_PENTIUM = 8;
+  UC_CPU_X86_PENTIUM2 = 9;
+  UC_CPU_X86_PENTIUM3 = 10;
+  UC_CPU_X86_ATHLON = 11;
+  UC_CPU_X86_N270 = 12;
+  UC_CPU_X86_CONROE = 13;
+  UC_CPU_X86_PENRYN = 14;
+  UC_CPU_X86_NEHALEM = 15;
+  UC_CPU_X86_WESTMERE = 16;
+  UC_CPU_X86_SANDYBRIDGE = 17;
+  UC_CPU_X86_IVYBRIDGE = 18;
+  UC_CPU_X86_HASWELL = 19;
+  UC_CPU_X86_BROADWELL = 20;
+  UC_CPU_X86_SKYLAKE_CLIENT = 21;
+  UC_CPU_X86_SKYLAKE_SERVER = 22;
+  UC_CPU_X86_CASCADELAKE_SERVER = 23;
+  UC_CPU_X86_COOPERLAKE = 24;
+  UC_CPU_X86_ICELAKE_CLIENT = 25;
+  UC_CPU_X86_ICELAKE_SERVER = 26;
+  UC_CPU_X86_DENVERTON = 27;
+  UC_CPU_X86_SNOWRIDGE = 28;
+  UC_CPU_X86_KNIGHTSMILL = 29;
+  UC_CPU_X86_OPTERON_G1 = 30;
+  UC_CPU_X86_OPTERON_G2 = 31;
+  UC_CPU_X86_OPTERON_G3 = 32;
+  UC_CPU_X86_OPTERON_G4 = 33;
+  UC_CPU_X86_OPTERON_G5 = 34;
+  UC_CPU_X86_EPYC = 35;
+  UC_CPU_X86_DHYANA = 36;
+  UC_CPU_X86_EPYC_ROME = 37;
+
 // X86 registers
 
   UC_X86_REG_INVALID = 0;

bindings/python/Makefile

@@ -3,16 +3,16 @@
 .PHONY: gen_const install install3 clean sdist sdist3 bdist bdist3 sdist_win bdist_win
 
 gen_const:
-	cd .. && python const_generator.py python
+	cd .. && python3 const_generator.py python
 
 install:
 	rm -rf src/ dist/
 	rm -rf prebuilt/win64/unicorn.dll
 	rm -rf prebuilt/win32/unicorn.dll
 	if test -n "${DESTDIR}"; then \
-		python setup.py install --root="${DESTDIR}"; \
+		python3 setup.py install --root="${DESTDIR}"; \
 	else \
-		python setup.py install; \
+		python3 setup.py install; \
 	fi
 
 install3:
@@ -30,7 +30,7 @@ sdist:
 	rm -rf src/ dist/
 	rm -rf prebuilt/win64/unicorn.dll
 	rm -rf prebuilt/win32/unicorn.dll
-	python setup.py sdist register upload
+	python3 setup.py sdist register upload
 
 # build & upload PyPi package with source code of the core
 sdist3:
@@ -44,7 +44,7 @@ bdist:
 	rm -rf src/ dist/
 	rm -rf prebuilt/win64/unicorn.dll
 	rm -rf prebuilt/win32/unicorn.dll
-	python setup.py bdist_wheel register upload
+	python3 setup.py bdist_wheel register upload
 
 # build & upload PyPi package with precompiled core
 bdist3:
@@ -57,7 +57,7 @@ bdist3:
 # NOTE: be sure to have precompiled core under prebuilt/win*/ beforehand
 sdist_win:
 	rm -rf src/ dist/
-	python setup.py sdist register upload
+	python3 setup.py sdist register upload
 
 # build & upload PyPi package with prebuilt core
 # NOTE: be sure to have precompiled core under prebuilt/win*/ beforehand

bindings/python/unicorn/arm64_const.py

@@ -1,5 +1,10 @@
 # For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm64_const.py]
 
+UC_CPU_AARCH64_A57 = 0
+UC_CPU_AARCH64_A53 = 1
+UC_CPU_AARCH64_A72 = 2
+UC_CPU_AARCH64_MAX = 3
+
 # ARM64 registers
 
 UC_ARM64_REG_INVALID = 0

bindings/python/unicorn/arm_const.py

@@ -1,5 +1,39 @@
 # For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm_const.py]
 
+UC_CPU_ARM_926 = 0
+UC_CPU_ARM_946 = 1
+UC_CPU_ARM_1026 = 2
+UC_CPU_ARM_1136_R2 = 3
+UC_CPU_ARM_1136 = 4
+UC_CPU_ARM_1176 = 5
+UC_CPU_ARM_11MPCORE = 6
+UC_CPU_ARM_CORTEX_M0 = 7
+UC_CPU_ARM_CORTEX_M3 = 8
+UC_CPU_ARM_CORTEX_M4 = 9
+UC_CPU_ARM_CORTEX_M7 = 10
+UC_CPU_ARM_CORTEX_M33 = 11
+UC_CPU_ARM_CORTEX_R5 = 12
+UC_CPU_ARM_CORTEX_R5F = 13
+UC_CPU_ARM_CORTEX_A8 = 14
+UC_CPU_ARM_CORTEX_A9 = 15
+UC_CPU_ARM_CORTEX_A7 = 16
+UC_CPU_ARM_CORTEX_A15 = 17
+UC_CPU_ARM_TI925T = 18
+UC_CPU_ARM_SA1100 = 19
+UC_CPU_ARM_SA1110 = 20
+UC_CPU_ARM_PXA250 = 21
+UC_CPU_ARM_PXA255 = 22
+UC_CPU_ARM_PXA260 = 23
+UC_CPU_ARM_PXA261 = 24
+UC_CPU_ARM_PXA262 = 25
+UC_CPU_ARM_PXA270A0 = 26
+UC_CPU_ARM_PXA270A1 = 27
+UC_CPU_ARM_PXA270B0 = 28
+UC_CPU_ARM_PXA270B1 = 29
+UC_CPU_ARM_PXA270C0 = 30
+UC_CPU_ARM_PXA270C5 = 31
+UC_CPU_ARM_MAX = 32
+
 # ARM registers
 
 UC_ARM_REG_INVALID = 0

bindings/python/unicorn/m68k_const.py

@@ -1,5 +1,15 @@
 # For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [m68k_const.py]
 
+UC_CPU_M5206_CPU = 0
+UC_CPU_M68000_CPU = 1
+UC_CPU_M68020_CPU = 2
+UC_CPU_M68030_CPU = 3
+UC_CPU_M68040_CPU = 4
+UC_CPU_M68060_CPU = 5
+UC_CPU_M5208_CPU = 6
+UC_CPU_CFV4E_CPU = 7
+UC_CPU_ANY_CPU = 8
+
 # M68K registers
 
 UC_M68K_REG_INVALID = 0

bindings/python/unicorn/mips_const.py

@@ -1,5 +1,35 @@
 # For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [mips_const.py]
 
+UC_CPU_MIPS_4KC = 0
+UC_CPU_MIPS_4KM = 1
+UC_CPU_MIPS_4KECR1 = 2
+UC_CPU_MIPS_4KEMR1 = 3
+UC_CPU_MIPS_4KEC = 4
+UC_CPU_MIPS_4KEM = 5
+UC_CPU_MIPS_24KC = 6
+UC_CPU_MIPS_24KEC = 7
+UC_CPU_MIPS_24KF = 8
+UC_CPU_MIPS_34KF = 9
+UC_CPU_MIPS_74KF = 10
+UC_CPU_MIPS_M14K = 11
+UC_CPU_MIPS_M14KC = 12
+UC_CPU_MIPS_P5600 = 13
+UC_CPU_MIPS_MIPS32R6_GENERIC = 14
+UC_CPU_MIPS_I7200 = 15
+UC_CPU_MIPS_R4000 = 16
+UC_CPU_MIPS_VR5432 = 17
+UC_CPU_MIPS_5KC = 18
+UC_CPU_MIPS_5KF = 19
+UC_CPU_MIPS_20KC = 20
+UC_CPU_MIPS_MIPS64R2_GENERIC = 21
+UC_CPU_MIPS_5KEC = 22
+UC_CPU_MIPS_5KEF = 23
+UC_CPU_MIPS_I6400 = 24
+UC_CPU_MIPS_I6500 = 25
+UC_CPU_MIPS_LOONGSON_2E = 26
+UC_CPU_MIPS_LOONGSON_2F = 27
+UC_CPU_MIPS_MIPS64DSPR2 = 28
+
 # MIPS registers
 
 UC_MIPS_REG_INVALID = 0

bindings/python/unicorn/ppc_const.py

@@ -1,5 +1,306 @@
 # For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [ppc_const.py]
 
+UC_CPU_PPC_401A1 = 0
+UC_CPU_PPC_401B2 = 1
+UC_CPU_PPC_401C2 = 2
+UC_CPU_PPC_401D2 = 3
+UC_CPU_PPC_401E2 = 4
+UC_CPU_PPC_401F2 = 5
+UC_CPU_PPC_401G2 = 6
+UC_CPU_PPC_COBRA = 7
+UC_CPU_PPC_403GA = 8
+UC_CPU_PPC_403GB = 9
+UC_CPU_PPC_403GC = 10
+UC_CPU_PPC_403GCX = 11
+UC_CPU_PPC_405D2 = 12
+UC_CPU_PPC_405D4 = 13
+UC_CPU_PPC_405CRA = 14
+UC_CPU_PPC_405CRB = 15
+UC_CPU_PPC_405CRC = 16
+UC_CPU_PPC_405EP = 17
+UC_CPU_PPC_405EZ = 18
+UC_CPU_PPC_405GPA = 19
+UC_CPU_PPC_405GPB = 20
+UC_CPU_PPC_405GPC = 21
+UC_CPU_PPC_405GPD = 22
+UC_CPU_PPC_405GPR = 23
+UC_CPU_PPC_405LP = 24
+UC_CPU_PPC_NPE405H = 25
+UC_CPU_PPC_NPE405H2 = 26
+UC_CPU_PPC_NPE405L = 27
+UC_CPU_PPC_NPE4GS3 = 28
+UC_CPU_PPC_STB03 = 29
+UC_CPU_PPC_STB04 = 30
+UC_CPU_PPC_STB25 = 31
+UC_CPU_PPC_X2VP4 = 32
+UC_CPU_PPC_440_XILINX = 33
+UC_CPU_PPC_440EPA = 34
+UC_CPU_PPC_440EPB = 35
+UC_CPU_PPC_440GPB = 36
+UC_CPU_PPC_440GPC = 37
+UC_CPU_PPC_440GRX = 38
+UC_CPU_PPC_440GXA = 39
+UC_CPU_PPC_440GXB = 40
+UC_CPU_PPC_440GXC = 41
+UC_CPU_PPC_440GXF = 42
+UC_CPU_PPC_440SP = 43
+UC_CPU_PPC_440SP2 = 44
+UC_CPU_PPC_440SPE = 45
+UC_CPU_PPC_460EXB = 46
+UC_CPU_PPC_MPC5XX = 47
+UC_CPU_PPC_MPC8XX = 48
+UC_CPU_PPC_G2 = 49
+UC_CPU_PPC_G2H4 = 50
+UC_CPU_PPC_G2GP = 51
+UC_CPU_PPC_G2LS = 52
+UC_CPU_PPC_MPC603 = 53
+UC_CPU_PPC_G2_HIP3 = 54
+UC_CPU_PPC_G2_HIP4 = 55
+UC_CPU_PPC_G2LE = 56
+UC_CPU_PPC_G2LEGP = 57
+UC_CPU_PPC_G2LELS = 58
+UC_CPU_PPC_G2LEGP1 = 59
+UC_CPU_PPC_G2LEGP3 = 60
+UC_CPU_PPC_E200Z5 = 61
+UC_CPU_PPC_E200Z6 = 62
+UC_CPU_PPC_E300C1 = 63
+UC_CPU_PPC_E300C2 = 64
+UC_CPU_PPC_E300C3 = 65
+UC_CPU_PPC_E300C4 = 66
+UC_CPU_PPC_E500V1_V10 = 67
+UC_CPU_PPC_E500V1_V20 = 68
+UC_CPU_PPC_E500V2_V10 = 69
+UC_CPU_PPC_E500V2_V11 = 70
+UC_CPU_PPC_E500V2_V20 = 71
+UC_CPU_PPC_E500V2_V21 = 72
+UC_CPU_PPC_E500V2_V22 = 73
+UC_CPU_PPC_E500V2_V30 = 74
+UC_CPU_PPC_E500MC = 75
+UC_CPU_PPC_E5500 = 76
+UC_CPU_PPC_E6500 = 77
+UC_CPU_PPC_E600 = 78
+UC_CPU_PPC_601_V0 = 79
+UC_CPU_PPC_601_V1 = 80
+UC_CPU_PPC_601_V2 = 81
+UC_CPU_PPC_602 = 82
+UC_CPU_PPC_603 = 83
+UC_CPU_PPC_603E_V11 = 84
+UC_CPU_PPC_603E_V12 = 85
+UC_CPU_PPC_603E_V13 = 86
+UC_CPU_PPC_603E_V14 = 87
+UC_CPU_PPC_603E_V22 = 88
+UC_CPU_PPC_603E_V3 = 89
+UC_CPU_PPC_603E_V4 = 90
+UC_CPU_PPC_603E_V41 = 91
+UC_CPU_PPC_603E7T = 92
+UC_CPU_PPC_603E7V = 93
+UC_CPU_PPC_603E7V1 = 94
+UC_CPU_PPC_603E7V2 = 95
+UC_CPU_PPC_603E7 = 96
+UC_CPU_PPC_603P = 97
+UC_CPU_PPC_604 = 98
+UC_CPU_PPC_604E_V10 = 99
+UC_CPU_PPC_604E_V22 = 100
+UC_CPU_PPC_604E_V24 = 101
+UC_CPU_PPC_604R = 102
+UC_CPU_PPC_7X0_V10 = 103
+UC_CPU_PPC_7X0_V20 = 104
+UC_CPU_PPC_7X0_V21 = 105
+UC_CPU_PPC_7X0_V22 = 106
+UC_CPU_PPC_7X0_V30 = 107
+UC_CPU_PPC_7X0_V31 = 108
+UC_CPU_PPC_740E = 109
+UC_CPU_PPC_750E = 110
+UC_CPU_PPC_7X0P = 111
+UC_CPU_PPC_750CL_V10 = 112
+UC_CPU_PPC_750CL_V20 = 113
+UC_CPU_PPC_750CX_V10 = 114
+UC_CPU_PPC_750CX_V20 = 115
+UC_CPU_PPC_750CX_V21 = 116
+UC_CPU_PPC_750CX_V22 = 117
+UC_CPU_PPC_750CXE_V21 = 118
+UC_CPU_PPC_750CXE_V22 = 119
+UC_CPU_PPC_750CXE_V23 = 120
+UC_CPU_PPC_750CXE_V24 = 121
+UC_CPU_PPC_750CXE_V24B = 122
+UC_CPU_PPC_750CXE_V30 = 123
+UC_CPU_PPC_750CXE_V31 = 124
+UC_CPU_PPC_750CXE_V31B = 125
+UC_CPU_PPC_750CXR = 126
+UC_CPU_PPC_750FL = 127
+UC_CPU_PPC_750FX_V10 = 128
+UC_CPU_PPC_750FX_V20 = 129
+UC_CPU_PPC_750FX_V21 = 130
+UC_CPU_PPC_750FX_V22 = 131
+UC_CPU_PPC_750FX_V23 = 132
+UC_CPU_PPC_750GL = 133
+UC_CPU_PPC_750GX_V10 = 134
+UC_CPU_PPC_750GX_V11 = 135
+UC_CPU_PPC_750GX_V12 = 136
+UC_CPU_PPC_750L_V20 = 137
+UC_CPU_PPC_750L_V21 = 138
+UC_CPU_PPC_750L_V22 = 139
+UC_CPU_PPC_750L_V30 = 140
+UC_CPU_PPC_750L_V32 = 141
+UC_CPU_PPC_7X5_V10 = 142
+UC_CPU_PPC_7X5_V11 = 143
+UC_CPU_PPC_7X5_V20 = 144
+UC_CPU_PPC_7X5_V21 = 145
+UC_CPU_PPC_7X5_V22 = 146
+UC_CPU_PPC_7X5_V23 = 147
+UC_CPU_PPC_7X5_V24 = 148
+UC_CPU_PPC_7X5_V25 = 149
+UC_CPU_PPC_7X5_V26 = 150
+UC_CPU_PPC_7X5_V27 = 151
+UC_CPU_PPC_7X5_V28 = 152
+UC_CPU_PPC_7400_V10 = 153
+UC_CPU_PPC_7400_V11 = 154
+UC_CPU_PPC_7400_V20 = 155
+UC_CPU_PPC_7400_V21 = 156
+UC_CPU_PPC_7400_V22 = 157
+UC_CPU_PPC_7400_V26 = 158
+UC_CPU_PPC_7400_V27 = 159
+UC_CPU_PPC_7400_V28 = 160
+UC_CPU_PPC_7400_V29 = 161
+UC_CPU_PPC_7410_V10 = 162
+UC_CPU_PPC_7410_V11 = 163
+UC_CPU_PPC_7410_V12 = 164
+UC_CPU_PPC_7410_V13 = 165
+UC_CPU_PPC_7410_V14 = 166
+UC_CPU_PPC_7448_V10 = 167
+UC_CPU_PPC_7448_V11 = 168
+UC_CPU_PPC_7448_V20 = 169
+UC_CPU_PPC_7448_V21 = 170
+UC_CPU_PPC_7450_V10 = 171
+UC_CPU_PPC_7450_V11 = 172
+UC_CPU_PPC_7450_V12 = 173
+UC_CPU_PPC_7450_V20 = 174
+UC_CPU_PPC_7450_V21 = 175
+UC_CPU_PPC_74X1_V23 = 176
+UC_CPU_PPC_74X1_V210 = 177
+UC_CPU_PPC_74X5_V10 = 178
+UC_CPU_PPC_74X5_V21 = 179
+UC_CPU_PPC_74X5_V32 = 180
+UC_CPU_PPC_74X5_V33 = 181
+UC_CPU_PPC_74X5_V34 = 182
+UC_CPU_PPC_74X7_V10 = 183
+UC_CPU_PPC_74X7_V11 = 184
+UC_CPU_PPC_74X7_V12 = 185
+UC_CPU_PPC_74X7A_V10 = 186
+UC_CPU_PPC_74X7A_V11 = 187
+UC_CPU_PPC_74X7A_V12 = 188
+UC_CPU_PPC_IOP480 = 1
+UC_CPU_PPC_X2VP20 = 42
+UC_CPU_PPC_440GRA = 35
+UC_CPU_PPC_440EPX = 38
+UC_CPU_PPC_MPC5200_V10 = 59
+UC_CPU_PPC_MPC5200_V11 = 59
+UC_CPU_PPC_MPC5200_V12 = 59
+UC_CPU_PPC_MPC5200B_V20 = 59
+UC_CPU_PPC_MPC5200B_V21 = 59
+UC_CPU_PPC_MPC834X = 63
+UC_CPU_PPC_MPC837X = 66
+UC_CPU_PPC_E500 = 73
+UC_CPU_PPC_MPC8533_V10 = 72
+UC_CPU_PPC_MPC8533_V11 = 73
+UC_CPU_PPC_MPC8533E_V10 = 72
+UC_CPU_PPC_MPC8533E_V11 = 73
+UC_CPU_PPC_MPC8540_V10 = 67
+UC_CPU_PPC_MPC8540_V20 = 68
+UC_CPU_PPC_MPC8540_V21 = 68
+UC_CPU_PPC_MPC8541_V10 = 68
+UC_CPU_PPC_MPC8541_V11 = 68
+UC_CPU_PPC_MPC8541E_V10 = 68
+UC_CPU_PPC_MPC8541E_V11 = 68
+UC_CPU_PPC_MPC8543_V10 = 69
+UC_CPU_PPC_MPC8543_V11 = 70
+UC_CPU_PPC_MPC8543_V20 = 71
+UC_CPU_PPC_MPC8543_V21 = 72
+UC_CPU_PPC_MPC8543E_V10 = 69
+UC_CPU_PPC_MPC8543E_V11 = 70
+UC_CPU_PPC_MPC8543E_V20 = 71
+UC_CPU_PPC_MPC8543E_V21 = 72
+UC_CPU_PPC_MPC8544_V10 = 72
+UC_CPU_PPC_MPC8544_V11 = 73
+UC_CPU_PPC_MPC8544E_V11 = 73
+UC_CPU_PPC_MPC8544E_V10 = 72
+UC_CPU_PPC_MPC8545_V10 = 69
+UC_CPU_PPC_MPC8545_V20 = 71
+UC_CPU_PPC_MPC8545_V21 = 72
+UC_CPU_PPC_MPC8545E_V10 = 69
+UC_CPU_PPC_MPC8545E_V20 = 71
+UC_CPU_PPC_MPC8545E_V21 = 72
+UC_CPU_PPC_MPC8547E_V10 = 69
+UC_CPU_PPC_MPC8547E_V20 = 71
+UC_CPU_PPC_MPC8547E_V21 = 72
+UC_CPU_PPC_MPC8548_V10 = 69
+UC_CPU_PPC_MPC8548_V11 = 70
+UC_CPU_PPC_MPC8548_V20 = 71
+UC_CPU_PPC_MPC8548_V21 = 72
+UC_CPU_PPC_MPC8548E_V10 = 69
+UC_CPU_PPC_MPC8548E_V11 = 70
+UC_CPU_PPC_MPC8548E_V20 = 71
+UC_CPU_PPC_MPC8548E_V21 = 72
+UC_CPU_PPC_MPC8555_V10 = 69
+UC_CPU_PPC_MPC8555_V11 = 70
+UC_CPU_PPC_MPC8555E_V10 = 69
+UC_CPU_PPC_MPC8555E_V11 = 70
+UC_CPU_PPC_MPC8560_V10 = 69
+UC_CPU_PPC_MPC8560_V20 = 71
+UC_CPU_PPC_MPC8560_V21 = 72
+UC_CPU_PPC_MPC8567 = 73
+UC_CPU_PPC_MPC8567E = 73
+UC_CPU_PPC_MPC8568 = 73
+UC_CPU_PPC_MPC8568E = 73
+UC_CPU_PPC_MPC8572 = 74
+UC_CPU_PPC_MPC8572E = 74
+UC_CPU_PPC_MPC8610 = 78
+UC_CPU_PPC_MPC8641 = 78
+UC_CPU_PPC_MPC8641D = 78
+
+UC_CPU_PPC64_620 = 0
+UC_CPU_PPC64_630 = 1
+UC_CPU_PPC64_631 = 2
+UC_CPU_PPC64_POWER4 = 3
+UC_CPU_PPC64_POWER4P = 4
+UC_CPU_PPC64_POWER5 = 5
+UC_CPU_PPC64_POWER5P_V21 = 6
+UC_CPU_PPC64_POWER6 = 7
+UC_CPU_PPC64_POWER_SERVER_MASK = 8
+UC_CPU_PPC64_POWER7_BASE = 9
+UC_CPU_PPC64_POWER7_V23 = 10
+UC_CPU_PPC64_POWER7P_BASE = 11
+UC_CPU_PPC64_POWER7P_V21 = 12
+UC_CPU_PPC64_POWER8E_BASE = 13
+UC_CPU_PPC64_POWER8E_V21 = 14
+UC_CPU_PPC64_POWER8_BASE = 15
+UC_CPU_PPC64_POWER8_V20 = 16
+UC_CPU_PPC64_POWER8NVL_BASE = 17
+UC_CPU_PPC64_POWER8NVL_V10 = 18
+UC_CPU_PPC64_POWER9_BASE = 19
+UC_CPU_PPC64_POWER9_DD1 = 20
+UC_CPU_PPC64_POWER9_DD20 = 21
+UC_CPU_PPC64_POWER10_BASE = 22
+UC_CPU_PPC64_POWER10_DD1 = 23
+UC_CPU_PPC64_970_V22 = 24
+UC_CPU_PPC64_970FX_V10 = 25
+UC_CPU_PPC64_970FX_V20 = 26
+UC_CPU_PPC64_970FX_V21 = 27
+UC_CPU_PPC64_970FX_V30 = 28
+UC_CPU_PPC64_970FX_V31 = 29
+UC_CPU_PPC64_970MP_V10 = 30
+UC_CPU_PPC64_970MP_V11 = 31
+UC_CPU_PPC64_CELL_V10 = 32
+UC_CPU_PPC64_CELL_V20 = 33
+UC_CPU_PPC64_CELL_V30 = 34
+UC_CPU_PPC64_CELL_V31 = 35
+UC_CPU_PPC64_RS64 = 36
+UC_CPU_PPC64_RS64II = 37
+UC_CPU_PPC64_RS64III = 38
+UC_CPU_PPC64_RS64IV = 39
+UC_CPU_PPC64_CELL_V32 = 35
+UC_CPU_PPC64_CELL = 35
+
 # PPC registers
 
 UC_PPC_REG_INVALID = 0

bindings/python/unicorn/riscv_const.py

@@ -1,5 +1,15 @@
 # For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [riscv_const.py]
 
+UC_CPU_RISCV32_ANY = 0
+UC_CPU_RISCV32_BASE32 = 1
+UC_CPU_RISCV32_SIFIVE_E31 = 2
+UC_CPU_RISCV32_SIFIVE_U34 = 3
+
+UC_CPU_RISCV64_ANY = 0
+UC_CPU_RISCV64_BASE64 = 1
+UC_CPU_RISCV64_SIFIVE_E51 = 2
+UC_CPU_RISCV64_SIFIVE_U54 = 3
+
 # RISCV registers
 
 UC_RISCV_REG_INVALID = 0

bindings/python/unicorn/sparc_const.py

@@ -1,5 +1,37 @@
 # For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [sparc_const.py]
 
+UC_CPU_SPARC_FUJITSU_MB86904 = 0
+UC_CPU_SPARC_FUJITSU_MB86907 = 1
+UC_CPU_SPARC_TI_MICROSPARC_I = 2
+UC_CPU_SPARC_TI_MICROSPARC_II = 3
+UC_CPU_SPARC_TI_MICROSPARC_IIEP = 4
+UC_CPU_SPARC_TI_SUPERSPARC_40 = 5
+UC_CPU_SPARC_TI_SUPERSPARC_50 = 6
+UC_CPU_SPARC_TI_SUPERSPARC_51 = 7
+UC_CPU_SPARC_TI_SUPERSPARC_60 = 8
+UC_CPU_SPARC_TI_SUPERSPARC_61 = 9
+UC_CPU_SPARC_TI_SUPERSPARC_II = 10
+UC_CPU_SPARC_LEON2 = 11
+UC_CPU_SPARC_LEON3 = 12
+
+UC_CPU_SPARC64_FUJITSU = 0
+UC_CPU_SPARC64_FUJITSU_III = 1
+UC_CPU_SPARC64_FUJITSU_IV = 2
+UC_CPU_SPARC64_FUJITSU_V = 3
+UC_CPU_SPARC64_TI_ULTRASPARC_I = 4
+UC_CPU_SPARC64_TI_ULTRASPARC_II = 5
+UC_CPU_SPARC64_TI_ULTRASPARC_III = 6
+UC_CPU_SPARC64_TI_ULTRASPARC_IIE = 7
+UC_CPU_SPARC64_SUN_ULTRASPARC_III = 8
+UC_CPU_SPARC64_SUN_ULTRASPARC_III_CU = 9
+UC_CPU_SPARC64_SUN_ULTRASPARC_IIII = 10
+UC_CPU_SPARC64_SUN_ULTRASPARC_IV = 11
+UC_CPU_SPARC64_SUN_ULTRASPARC_IV_PLUS = 12
+UC_CPU_SPARC64_SUN_ULTRASPARC_IIII_PLUS = 13
+UC_CPU_SPARC64_SUN_ULTRASPARC_T1 = 14
+UC_CPU_SPARC64_SUN_ULTRASPARC_T2 = 15
+UC_CPU_SPARC64_NEC_ULTRASPARC_I = 16
+
 # SPARC registers
 
 UC_SPARC_REG_INVALID = 0

bindings/python/unicorn/unicorn_const.py

@@ -105,6 +105,22 @@ UC_QUERY_PAGE_SIZE = 2
 UC_QUERY_ARCH = 3
 UC_QUERY_TIMEOUT = 4
 
+UC_CTL_IO_NONE = 0
+UC_CTL_IO_WRITE = 1
+UC_CTL_IO_READ = 2
+UC_CTL_IO_READ_WRITE = 3
+
+UC_CTL_UC_MODE = 0
+UC_CTL_UC_PAGE_SIZE = 1
+UC_CTL_UC_ARCH = 2
+UC_CTL_UC_TIMEOUT = 3
+UC_CTL_UC_EXITS_CNT = 4
+UC_CTL_UC_EXITS = 5
+UC_CTL_CPU_MODEL = 6
+UC_CTL_TB_EDGE = 7
+UC_CTL_TB_REQUEST_CACHE = 8
+UC_CTL_TB_REMOVE_CACHE = 9
+
 UC_PROT_NONE = 0
 UC_PROT_READ = 1
 UC_PROT_WRITE = 2

bindings/python/unicorn/x86_const.py

@@ -1,5 +1,44 @@
 # For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT [x86_const.py]
 
+UC_CPU_X86_QEMU64 = 0
+UC_CPU_X86_PHENOM = 1
+UC_CPU_X86_CORE2DUO = 2
+UC_CPU_X86_KVM64 = 3
+UC_CPU_X86_QEMU32 = 4
+UC_CPU_X86_KVM32 = 5
+UC_CPU_X86_COREDUO = 6
+UC_CPU_X86_486 = 7
+UC_CPU_X86_PENTIUM = 8
+UC_CPU_X86_PENTIUM2 = 9
+UC_CPU_X86_PENTIUM3 = 10
+UC_CPU_X86_ATHLON = 11
+UC_CPU_X86_N270 = 12
+UC_CPU_X86_CONROE = 13
+UC_CPU_X86_PENRYN = 14
+UC_CPU_X86_NEHALEM = 15
+UC_CPU_X86_WESTMERE = 16
+UC_CPU_X86_SANDYBRIDGE = 17
+UC_CPU_X86_IVYBRIDGE = 18
+UC_CPU_X86_HASWELL = 19
+UC_CPU_X86_BROADWELL = 20
+UC_CPU_X86_SKYLAKE_CLIENT = 21
+UC_CPU_X86_SKYLAKE_SERVER = 22
+UC_CPU_X86_CASCADELAKE_SERVER = 23
+UC_CPU_X86_COOPERLAKE = 24
+UC_CPU_X86_ICELAKE_CLIENT = 25
+UC_CPU_X86_ICELAKE_SERVER = 26
+UC_CPU_X86_DENVERTON = 27
+UC_CPU_X86_SNOWRIDGE = 28
+UC_CPU_X86_KNIGHTSMILL = 29
+UC_CPU_X86_OPTERON_G1 = 30
+UC_CPU_X86_OPTERON_G2 = 31
+UC_CPU_X86_OPTERON_G3 = 32
+UC_CPU_X86_OPTERON_G4 = 33
+UC_CPU_X86_OPTERON_G5 = 34
+UC_CPU_X86_EPYC = 35
+UC_CPU_X86_DHYANA = 36
+UC_CPU_X86_EPYC_ROME = 37
+
 # X86 registers
 
 UC_X86_REG_INVALID = 0

bindings/ruby/Makefile

@@ -8,4 +8,4 @@ install: gen_const
 	cd unicorn_gem && gem install --local pkg/unicorn-engine-1.0.1.gem
 
 gen_const:
-	cd .. && python const_generator.py ruby
+	cd .. && python3 const_generator.py ruby

bindings/ruby/unicorn_gem/lib/unicorn_engine/arm64_const.rb

@@ -2,6 +2,11 @@
 
 module UnicornEngine
 
+	UC_CPU_AARCH64_A57 = 0
+	UC_CPU_AARCH64_A53 = 1
+	UC_CPU_AARCH64_A72 = 2
+	UC_CPU_AARCH64_MAX = 3
+
 # ARM64 registers
 
 	UC_ARM64_REG_INVALID = 0

bindings/ruby/unicorn_gem/lib/unicorn_engine/arm_const.rb

@@ -2,6 +2,40 @@
 
 module UnicornEngine
 
+	UC_CPU_ARM_926 = 0
+	UC_CPU_ARM_946 = 1
+	UC_CPU_ARM_1026 = 2
+	UC_CPU_ARM_1136_R2 = 3
+	UC_CPU_ARM_1136 = 4
+	UC_CPU_ARM_1176 = 5
+	UC_CPU_ARM_11MPCORE = 6
+	UC_CPU_ARM_CORTEX_M0 = 7
+	UC_CPU_ARM_CORTEX_M3 = 8
+	UC_CPU_ARM_CORTEX_M4 = 9
+	UC_CPU_ARM_CORTEX_M7 = 10
+	UC_CPU_ARM_CORTEX_M33 = 11
+	UC_CPU_ARM_CORTEX_R5 = 12
+	UC_CPU_ARM_CORTEX_R5F = 13
+	UC_CPU_ARM_CORTEX_A8 = 14
+	UC_CPU_ARM_CORTEX_A9 = 15
+	UC_CPU_ARM_CORTEX_A7 = 16
+	UC_CPU_ARM_CORTEX_A15 = 17
+	UC_CPU_ARM_TI925T = 18
+	UC_CPU_ARM_SA1100 = 19
+	UC_CPU_ARM_SA1110 = 20
+	UC_CPU_ARM_PXA250 = 21
+	UC_CPU_ARM_PXA255 = 22
+	UC_CPU_ARM_PXA260 = 23
+	UC_CPU_ARM_PXA261 = 24
+	UC_CPU_ARM_PXA262 = 25
+	UC_CPU_ARM_PXA270A0 = 26
+	UC_CPU_ARM_PXA270A1 = 27
+	UC_CPU_ARM_PXA270B0 = 28
+	UC_CPU_ARM_PXA270B1 = 29
+	UC_CPU_ARM_PXA270C0 = 30
+	UC_CPU_ARM_PXA270C5 = 31
+	UC_CPU_ARM_MAX = 32
+
 # ARM registers
 
 	UC_ARM_REG_INVALID = 0

bindings/ruby/unicorn_gem/lib/unicorn_engine/m68k_const.rb

@@ -2,6 +2,16 @@
 
 module UnicornEngine
 
+	UC_CPU_M5206_CPU = 0
+	UC_CPU_M68000_CPU = 1
+	UC_CPU_M68020_CPU = 2
+	UC_CPU_M68030_CPU = 3
+	UC_CPU_M68040_CPU = 4
+	UC_CPU_M68060_CPU = 5
+	UC_CPU_M5208_CPU = 6
+	UC_CPU_CFV4E_CPU = 7
+	UC_CPU_ANY_CPU = 8
+
 # M68K registers
 
 	UC_M68K_REG_INVALID = 0

bindings/ruby/unicorn_gem/lib/unicorn_engine/mips_const.rb

@@ -2,6 +2,36 @@
 
 module UnicornEngine
 
+	UC_CPU_MIPS_4KC = 0
+	UC_CPU_MIPS_4KM = 1
+	UC_CPU_MIPS_4KECR1 = 2
+	UC_CPU_MIPS_4KEMR1 = 3
+	UC_CPU_MIPS_4KEC = 4
+	UC_CPU_MIPS_4KEM = 5
+	UC_CPU_MIPS_24KC = 6
+	UC_CPU_MIPS_24KEC = 7
+	UC_CPU_MIPS_24KF = 8
+	UC_CPU_MIPS_34KF = 9
+	UC_CPU_MIPS_74KF = 10
+	UC_CPU_MIPS_M14K = 11
+	UC_CPU_MIPS_M14KC = 12
+	UC_CPU_MIPS_P5600 = 13
+	UC_CPU_MIPS_MIPS32R6_GENERIC = 14
+	UC_CPU_MIPS_I7200 = 15
+	UC_CPU_MIPS_R4000 = 16
+	UC_CPU_MIPS_VR5432 = 17
+	UC_CPU_MIPS_5KC = 18
+	UC_CPU_MIPS_5KF = 19
+	UC_CPU_MIPS_20KC = 20
+	UC_CPU_MIPS_MIPS64R2_GENERIC = 21
+	UC_CPU_MIPS_5KEC = 22
+	UC_CPU_MIPS_5KEF = 23
+	UC_CPU_MIPS_I6400 = 24
+	UC_CPU_MIPS_I6500 = 25
+	UC_CPU_MIPS_LOONGSON_2E = 26
+	UC_CPU_MIPS_LOONGSON_2F = 27
+	UC_CPU_MIPS_MIPS64DSPR2 = 28
+
 # MIPS registers
 
 	UC_MIPS_REG_INVALID = 0

bindings/ruby/unicorn_gem/lib/unicorn_engine/ppc_const.rb

@@ -2,6 +2,307 @@
 
 module UnicornEngine
 
+	UC_CPU_PPC_401A1 = 0
+	UC_CPU_PPC_401B2 = 1
+	UC_CPU_PPC_401C2 = 2
+	UC_CPU_PPC_401D2 = 3
+	UC_CPU_PPC_401E2 = 4
+	UC_CPU_PPC_401F2 = 5
+	UC_CPU_PPC_401G2 = 6
+	UC_CPU_PPC_COBRA = 7
+	UC_CPU_PPC_403GA = 8
+	UC_CPU_PPC_403GB = 9
+	UC_CPU_PPC_403GC = 10
+	UC_CPU_PPC_403GCX = 11
+	UC_CPU_PPC_405D2 = 12
+	UC_CPU_PPC_405D4 = 13
+	UC_CPU_PPC_405CRA = 14
+	UC_CPU_PPC_405CRB = 15
+	UC_CPU_PPC_405CRC = 16
+	UC_CPU_PPC_405EP = 17
+	UC_CPU_PPC_405EZ = 18
+	UC_CPU_PPC_405GPA = 19
+	UC_CPU_PPC_405GPB = 20
+	UC_CPU_PPC_405GPC = 21
+	UC_CPU_PPC_405GPD = 22
+	UC_CPU_PPC_405GPR = 23
+	UC_CPU_PPC_405LP = 24
+	UC_CPU_PPC_NPE405H = 25
+	UC_CPU_PPC_NPE405H2 = 26
+	UC_CPU_PPC_NPE405L = 27
+	UC_CPU_PPC_NPE4GS3 = 28
+	UC_CPU_PPC_STB03 = 29
+	UC_CPU_PPC_STB04 = 30
+	UC_CPU_PPC_STB25 = 31
+	UC_CPU_PPC_X2VP4 = 32
+	UC_CPU_PPC_440_XILINX = 33
+	UC_CPU_PPC_440EPA = 34
+	UC_CPU_PPC_440EPB = 35
+	UC_CPU_PPC_440GPB = 36
+	UC_CPU_PPC_440GPC = 37
+	UC_CPU_PPC_440GRX = 38
+	UC_CPU_PPC_440GXA = 39
+	UC_CPU_PPC_440GXB = 40
+	UC_CPU_PPC_440GXC = 41
+	UC_CPU_PPC_440GXF = 42
+	UC_CPU_PPC_440SP = 43
+	UC_CPU_PPC_440SP2 = 44
+	UC_CPU_PPC_440SPE = 45
+	UC_CPU_PPC_460EXB = 46
+	UC_CPU_PPC_MPC5XX = 47
+	UC_CPU_PPC_MPC8XX = 48
+	UC_CPU_PPC_G2 = 49
+	UC_CPU_PPC_G2H4 = 50
+	UC_CPU_PPC_G2GP = 51
+	UC_CPU_PPC_G2LS = 52
+	UC_CPU_PPC_MPC603 = 53
+	UC_CPU_PPC_G2_HIP3 = 54
+	UC_CPU_PPC_G2_HIP4 = 55
+	UC_CPU_PPC_G2LE = 56
+	UC_CPU_PPC_G2LEGP = 57
+	UC_CPU_PPC_G2LELS = 58
+	UC_CPU_PPC_G2LEGP1 = 59
+	UC_CPU_PPC_G2LEGP3 = 60
+	UC_CPU_PPC_E200Z5 = 61
+	UC_CPU_PPC_E200Z6 = 62
+	UC_CPU_PPC_E300C1 = 63
+	UC_CPU_PPC_E300C2 = 64
+	UC_CPU_PPC_E300C3 = 65
+	UC_CPU_PPC_E300C4 = 66
+	UC_CPU_PPC_E500V1_V10 = 67
+	UC_CPU_PPC_E500V1_V20 = 68
+	UC_CPU_PPC_E500V2_V10 = 69
+	UC_CPU_PPC_E500V2_V11 = 70
+	UC_CPU_PPC_E500V2_V20 = 71
+	UC_CPU_PPC_E500V2_V21 = 72
+	UC_CPU_PPC_E500V2_V22 = 73
+	UC_CPU_PPC_E500V2_V30 = 74
+	UC_CPU_PPC_E500MC = 75
+	UC_CPU_PPC_E5500 = 76
+	UC_CPU_PPC_E6500 = 77
+	UC_CPU_PPC_E600 = 78
+	UC_CPU_PPC_601_V0 = 79
+	UC_CPU_PPC_601_V1 = 80
+	UC_CPU_PPC_601_V2 = 81
+	UC_CPU_PPC_602 = 82
+	UC_CPU_PPC_603 = 83
+	UC_CPU_PPC_603E_V11 = 84
+	UC_CPU_PPC_603E_V12 = 85
+	UC_CPU_PPC_603E_V13 = 86
+	UC_CPU_PPC_603E_V14 = 87
+	UC_CPU_PPC_603E_V22 = 88
+	UC_CPU_PPC_603E_V3 = 89
+	UC_CPU_PPC_603E_V4 = 90
+	UC_CPU_PPC_603E_V41 = 91
+	UC_CPU_PPC_603E7T = 92
+	UC_CPU_PPC_603E7V = 93
+	UC_CPU_PPC_603E7V1 = 94
+	UC_CPU_PPC_603E7V2 = 95
+	UC_CPU_PPC_603E7 = 96
+	UC_CPU_PPC_603P = 97
+	UC_CPU_PPC_604 = 98
+	UC_CPU_PPC_604E_V10 = 99
+	UC_CPU_PPC_604E_V22 = 100
+	UC_CPU_PPC_604E_V24 = 101
+	UC_CPU_PPC_604R = 102
+	UC_CPU_PPC_7X0_V10 = 103
+	UC_CPU_PPC_7X0_V20 = 104
+	UC_CPU_PPC_7X0_V21 = 105
+	UC_CPU_PPC_7X0_V22 = 106
+	UC_CPU_PPC_7X0_V30 = 107
+	UC_CPU_PPC_7X0_V31 = 108
+	UC_CPU_PPC_740E = 109
+	UC_CPU_PPC_750E = 110
+	UC_CPU_PPC_7X0P = 111
+	UC_CPU_PPC_750CL_V10 = 112
+	UC_CPU_PPC_750CL_V20 = 113
+	UC_CPU_PPC_750CX_V10 = 114
+	UC_CPU_PPC_750CX_V20 = 115
+	UC_CPU_PPC_750CX_V21 = 116
+	UC_CPU_PPC_750CX_V22 = 117
+	UC_CPU_PPC_750CXE_V21 = 118
+	UC_CPU_PPC_750CXE_V22 = 119
+	UC_CPU_PPC_750CXE_V23 = 120
+	UC_CPU_PPC_750CXE_V24 = 121
+	UC_CPU_PPC_750CXE_V24B = 122
+	UC_CPU_PPC_750CXE_V30 = 123
+	UC_CPU_PPC_750CXE_V31 = 124
+	UC_CPU_PPC_750CXE_V31B = 125
+	UC_CPU_PPC_750CXR = 126
+	UC_CPU_PPC_750FL = 127
+	UC_CPU_PPC_750FX_V10 = 128
+	UC_CPU_PPC_750FX_V20 = 129
+	UC_CPU_PPC_750FX_V21 = 130
+	UC_CPU_PPC_750FX_V22 = 131
+	UC_CPU_PPC_750FX_V23 = 132
+	UC_CPU_PPC_750GL = 133
+	UC_CPU_PPC_750GX_V10 = 134
+	UC_CPU_PPC_750GX_V11 = 135
+	UC_CPU_PPC_750GX_V12 = 136
+	UC_CPU_PPC_750L_V20 = 137
+	UC_CPU_PPC_750L_V21 = 138
+	UC_CPU_PPC_750L_V22 = 139
+	UC_CPU_PPC_750L_V30 = 140
+	UC_CPU_PPC_750L_V32 = 141
+	UC_CPU_PPC_7X5_V10 = 142
+	UC_CPU_PPC_7X5_V11 = 143
+	UC_CPU_PPC_7X5_V20 = 144
+	UC_CPU_PPC_7X5_V21 = 145
+	UC_CPU_PPC_7X5_V22 = 146
+	UC_CPU_PPC_7X5_V23 = 147
+	UC_CPU_PPC_7X5_V24 = 148
+	UC_CPU_PPC_7X5_V25 = 149
+	UC_CPU_PPC_7X5_V26 = 150
+	UC_CPU_PPC_7X5_V27 = 151
+	UC_CPU_PPC_7X5_V28 = 152
+	UC_CPU_PPC_7400_V10 = 153
+	UC_CPU_PPC_7400_V11 = 154
+	UC_CPU_PPC_7400_V20 = 155
+	UC_CPU_PPC_7400_V21 = 156
+	UC_CPU_PPC_7400_V22 = 157
+	UC_CPU_PPC_7400_V26 = 158
+	UC_CPU_PPC_7400_V27 = 159
+	UC_CPU_PPC_7400_V28 = 160
+	UC_CPU_PPC_7400_V29 = 161
+	UC_CPU_PPC_7410_V10 = 162
+	UC_CPU_PPC_7410_V11 = 163
+	UC_CPU_PPC_7410_V12 = 164
+	UC_CPU_PPC_7410_V13 = 165
+	UC_CPU_PPC_7410_V14 = 166
+	UC_CPU_PPC_7448_V10 = 167
+	UC_CPU_PPC_7448_V11 = 168
+	UC_CPU_PPC_7448_V20 = 169
+	UC_CPU_PPC_7448_V21 = 170
+	UC_CPU_PPC_7450_V10 = 171
+	UC_CPU_PPC_7450_V11 = 172
+	UC_CPU_PPC_7450_V12 = 173
+	UC_CPU_PPC_7450_V20 = 174
+	UC_CPU_PPC_7450_V21 = 175
+	UC_CPU_PPC_74X1_V23 = 176
+	UC_CPU_PPC_74X1_V210 = 177
+	UC_CPU_PPC_74X5_V10 = 178
+	UC_CPU_PPC_74X5_V21 = 179
+	UC_CPU_PPC_74X5_V32 = 180
+	UC_CPU_PPC_74X5_V33 = 181
+	UC_CPU_PPC_74X5_V34 = 182
+	UC_CPU_PPC_74X7_V10 = 183
+	UC_CPU_PPC_74X7_V11 = 184
+	UC_CPU_PPC_74X7_V12 = 185
+	UC_CPU_PPC_74X7A_V10 = 186
+	UC_CPU_PPC_74X7A_V11 = 187
+	UC_CPU_PPC_74X7A_V12 = 188
+	UC_CPU_PPC_IOP480 = 1
+	UC_CPU_PPC_X2VP20 = 42
+	UC_CPU_PPC_440GRA = 35
+	UC_CPU_PPC_440EPX = 38
+	UC_CPU_PPC_MPC5200_V10 = 59
+	UC_CPU_PPC_MPC5200_V11 = 59
+	UC_CPU_PPC_MPC5200_V12 = 59
+	UC_CPU_PPC_MPC5200B_V20 = 59
+	UC_CPU_PPC_MPC5200B_V21 = 59
+	UC_CPU_PPC_MPC834X = 63
+	UC_CPU_PPC_MPC837X = 66
+	UC_CPU_PPC_E500 = 73
+	UC_CPU_PPC_MPC8533_V10 = 72
+	UC_CPU_PPC_MPC8533_V11 = 73
+	UC_CPU_PPC_MPC8533E_V10 = 72
+	UC_CPU_PPC_MPC8533E_V11 = 73
+	UC_CPU_PPC_MPC8540_V10 = 67
+	UC_CPU_PPC_MPC8540_V20 = 68
+	UC_CPU_PPC_MPC8540_V21 = 68
+	UC_CPU_PPC_MPC8541_V10 = 68
+	UC_CPU_PPC_MPC8541_V11 = 68
+	UC_CPU_PPC_MPC8541E_V10 = 68
+	UC_CPU_PPC_MPC8541E_V11 = 68
+	UC_CPU_PPC_MPC8543_V10 = 69
+	UC_CPU_PPC_MPC8543_V11 = 70
+	UC_CPU_PPC_MPC8543_V20 = 71
+	UC_CPU_PPC_MPC8543_V21 = 72
+	UC_CPU_PPC_MPC8543E_V10 = 69
+	UC_CPU_PPC_MPC8543E_V11 = 70
+	UC_CPU_PPC_MPC8543E_V20 = 71
+	UC_CPU_PPC_MPC8543E_V21 = 72
+	UC_CPU_PPC_MPC8544_V10 = 72
+	UC_CPU_PPC_MPC8544_V11 = 73
+	UC_CPU_PPC_MPC8544E_V11 = 73
+	UC_CPU_PPC_MPC8544E_V10 = 72
+	UC_CPU_PPC_MPC8545_V10 = 69
+	UC_CPU_PPC_MPC8545_V20 = 71
+	UC_CPU_PPC_MPC8545_V21 = 72
+	UC_CPU_PPC_MPC8545E_V10 = 69
+	UC_CPU_PPC_MPC8545E_V20 = 71
+	UC_CPU_PPC_MPC8545E_V21 = 72
+	UC_CPU_PPC_MPC8547E_V10 = 69
+	UC_CPU_PPC_MPC8547E_V20 = 71
+	UC_CPU_PPC_MPC8547E_V21 = 72
+	UC_CPU_PPC_MPC8548_V10 = 69
+	UC_CPU_PPC_MPC8548_V11 = 70
+	UC_CPU_PPC_MPC8548_V20 = 71
+	UC_CPU_PPC_MPC8548_V21 = 72
+	UC_CPU_PPC_MPC8548E_V10 = 69
+	UC_CPU_PPC_MPC8548E_V11 = 70
+	UC_CPU_PPC_MPC8548E_V20 = 71
+	UC_CPU_PPC_MPC8548E_V21 = 72
+	UC_CPU_PPC_MPC8555_V10 = 69
+	UC_CPU_PPC_MPC8555_V11 = 70
+	UC_CPU_PPC_MPC8555E_V10 = 69
+	UC_CPU_PPC_MPC8555E_V11 = 70
+	UC_CPU_PPC_MPC8560_V10 = 69
+	UC_CPU_PPC_MPC8560_V20 = 71
+	UC_CPU_PPC_MPC8560_V21 = 72
+	UC_CPU_PPC_MPC8567 = 73
+	UC_CPU_PPC_MPC8567E = 73
+	UC_CPU_PPC_MPC8568 = 73
+	UC_CPU_PPC_MPC8568E = 73
+	UC_CPU_PPC_MPC8572 = 74
+	UC_CPU_PPC_MPC8572E = 74
+	UC_CPU_PPC_MPC8610 = 78
+	UC_CPU_PPC_MPC8641 = 78
+	UC_CPU_PPC_MPC8641D = 78
+
+	UC_CPU_PPC64_620 = 0
+	UC_CPU_PPC64_630 = 1
+	UC_CPU_PPC64_631 = 2
+	UC_CPU_PPC64_POWER4 = 3
+	UC_CPU_PPC64_POWER4P = 4
+	UC_CPU_PPC64_POWER5 = 5
+	UC_CPU_PPC64_POWER5P_V21 = 6
+	UC_CPU_PPC64_POWER6 = 7
+	UC_CPU_PPC64_POWER_SERVER_MASK = 8
+	UC_CPU_PPC64_POWER7_BASE = 9
+	UC_CPU_PPC64_POWER7_V23 = 10
+	UC_CPU_PPC64_POWER7P_BASE = 11
+	UC_CPU_PPC64_POWER7P_V21 = 12
+	UC_CPU_PPC64_POWER8E_BASE = 13
+	UC_CPU_PPC64_POWER8E_V21 = 14
+	UC_CPU_PPC64_POWER8_BASE = 15
+	UC_CPU_PPC64_POWER8_V20 = 16
+	UC_CPU_PPC64_POWER8NVL_BASE = 17
+	UC_CPU_PPC64_POWER8NVL_V10 = 18
+	UC_CPU_PPC64_POWER9_BASE = 19
+	UC_CPU_PPC64_POWER9_DD1 = 20
+	UC_CPU_PPC64_POWER9_DD20 = 21
+	UC_CPU_PPC64_POWER10_BASE = 22
+	UC_CPU_PPC64_POWER10_DD1 = 23
+	UC_CPU_PPC64_970_V22 = 24
+	UC_CPU_PPC64_970FX_V10 = 25
+	UC_CPU_PPC64_970FX_V20 = 26
+	UC_CPU_PPC64_970FX_V21 = 27
+	UC_CPU_PPC64_970FX_V30 = 28
+	UC_CPU_PPC64_970FX_V31 = 29
+	UC_CPU_PPC64_970MP_V10 = 30
+	UC_CPU_PPC64_970MP_V11 = 31
+	UC_CPU_PPC64_CELL_V10 = 32
+	UC_CPU_PPC64_CELL_V20 = 33
+	UC_CPU_PPC64_CELL_V30 = 34
+	UC_CPU_PPC64_CELL_V31 = 35
+	UC_CPU_PPC64_RS64 = 36
+	UC_CPU_PPC64_RS64II = 37
+	UC_CPU_PPC64_RS64III = 38
+	UC_CPU_PPC64_RS64IV = 39
+	UC_CPU_PPC64_CELL_V32 = 35
+	UC_CPU_PPC64_CELL = 35
+
 # PPC registers
 
 	UC_PPC_REG_INVALID = 0

bindings/ruby/unicorn_gem/lib/unicorn_engine/riscv_const.rb

@@ -2,6 +2,16 @@
 
 module UnicornEngine
 
+	UC_CPU_RISCV32_ANY = 0
+	UC_CPU_RISCV32_BASE32 = 1
+	UC_CPU_RISCV32_SIFIVE_E31 = 2
+	UC_CPU_RISCV32_SIFIVE_U34 = 3
+
+	UC_CPU_RISCV64_ANY = 0
+	UC_CPU_RISCV64_BASE64 = 1
+	UC_CPU_RISCV64_SIFIVE_E51 = 2
+	UC_CPU_RISCV64_SIFIVE_U54 = 3
+
 # RISCV registers
 
 	UC_RISCV_REG_INVALID = 0

bindings/ruby/unicorn_gem/lib/unicorn_engine/sparc_const.rb

@@ -2,6 +2,38 @@
 
 module UnicornEngine
 
+	UC_CPU_SPARC_FUJITSU_MB86904 = 0
+	UC_CPU_SPARC_FUJITSU_MB86907 = 1
+	UC_CPU_SPARC_TI_MICROSPARC_I = 2
+	UC_CPU_SPARC_TI_MICROSPARC_II = 3
+	UC_CPU_SPARC_TI_MICROSPARC_IIEP = 4
+	UC_CPU_SPARC_TI_SUPERSPARC_40 = 5
+	UC_CPU_SPARC_TI_SUPERSPARC_50 = 6
+	UC_CPU_SPARC_TI_SUPERSPARC_51 = 7
+	UC_CPU_SPARC_TI_SUPERSPARC_60 = 8
+	UC_CPU_SPARC_TI_SUPERSPARC_61 = 9
+	UC_CPU_SPARC_TI_SUPERSPARC_II = 10
+	UC_CPU_SPARC_LEON2 = 11
+	UC_CPU_SPARC_LEON3 = 12
+
+	UC_CPU_SPARC64_FUJITSU = 0
+	UC_CPU_SPARC64_FUJITSU_III = 1
+	UC_CPU_SPARC64_FUJITSU_IV = 2
+	UC_CPU_SPARC64_FUJITSU_V = 3
+	UC_CPU_SPARC64_TI_ULTRASPARC_I = 4
+	UC_CPU_SPARC64_TI_ULTRASPARC_II = 5
+	UC_CPU_SPARC64_TI_ULTRASPARC_III = 6
+	UC_CPU_SPARC64_TI_ULTRASPARC_IIE = 7
+	UC_CPU_SPARC64_SUN_ULTRASPARC_III = 8
+	UC_CPU_SPARC64_SUN_ULTRASPARC_III_CU = 9
+	UC_CPU_SPARC64_SUN_ULTRASPARC_IIII = 10
+	UC_CPU_SPARC64_SUN_ULTRASPARC_IV = 11
+	UC_CPU_SPARC64_SUN_ULTRASPARC_IV_PLUS = 12
+	UC_CPU_SPARC64_SUN_ULTRASPARC_IIII_PLUS = 13
+	UC_CPU_SPARC64_SUN_ULTRASPARC_T1 = 14
+	UC_CPU_SPARC64_SUN_ULTRASPARC_T2 = 15
+	UC_CPU_SPARC64_NEC_ULTRASPARC_I = 16
+
 # SPARC registers
 
 	UC_SPARC_REG_INVALID = 0

bindings/ruby/unicorn_gem/lib/unicorn_engine/unicorn_const.rb

@@ -107,6 +107,22 @@ module UnicornEngine
 	UC_QUERY_ARCH = 3
 	UC_QUERY_TIMEOUT = 4
 
+	UC_CTL_IO_NONE = 0
+	UC_CTL_IO_WRITE = 1
+	UC_CTL_IO_READ = 2
+	UC_CTL_IO_READ_WRITE = 3
+
+	UC_CTL_UC_MODE = 0
+	UC_CTL_UC_PAGE_SIZE = 1
+	UC_CTL_UC_ARCH = 2
+	UC_CTL_UC_TIMEOUT = 3
+	UC_CTL_UC_EXITS_CNT = 4
+	UC_CTL_UC_EXITS = 5
+	UC_CTL_CPU_MODEL = 6
+	UC_CTL_TB_EDGE = 7
+	UC_CTL_TB_REQUEST_CACHE = 8
+	UC_CTL_TB_REMOVE_CACHE = 9
+
 	UC_PROT_NONE = 0
 	UC_PROT_READ = 1
 	UC_PROT_WRITE = 2

bindings/ruby/unicorn_gem/lib/unicorn_engine/x86_const.rb

@@ -2,6 +2,45 @@
 
 module UnicornEngine
 
+	UC_CPU_X86_QEMU64 = 0
+	UC_CPU_X86_PHENOM = 1
+	UC_CPU_X86_CORE2DUO = 2
+	UC_CPU_X86_KVM64 = 3
+	UC_CPU_X86_QEMU32 = 4
+	UC_CPU_X86_KVM32 = 5
+	UC_CPU_X86_COREDUO = 6
+	UC_CPU_X86_486 = 7
+	UC_CPU_X86_PENTIUM = 8
+	UC_CPU_X86_PENTIUM2 = 9
+	UC_CPU_X86_PENTIUM3 = 10
+	UC_CPU_X86_ATHLON = 11
+	UC_CPU_X86_N270 = 12
+	UC_CPU_X86_CONROE = 13
+	UC_CPU_X86_PENRYN = 14
+	UC_CPU_X86_NEHALEM = 15
+	UC_CPU_X86_WESTMERE = 16
+	UC_CPU_X86_SANDYBRIDGE = 17
+	UC_CPU_X86_IVYBRIDGE = 18
+	UC_CPU_X86_HASWELL = 19
+	UC_CPU_X86_BROADWELL = 20
+	UC_CPU_X86_SKYLAKE_CLIENT = 21
+	UC_CPU_X86_SKYLAKE_SERVER = 22
+	UC_CPU_X86_CASCADELAKE_SERVER = 23
+	UC_CPU_X86_COOPERLAKE = 24
+	UC_CPU_X86_ICELAKE_CLIENT = 25
+	UC_CPU_X86_ICELAKE_SERVER = 26
+	UC_CPU_X86_DENVERTON = 27
+	UC_CPU_X86_SNOWRIDGE = 28
+	UC_CPU_X86_KNIGHTSMILL = 29
+	UC_CPU_X86_OPTERON_G1 = 30
+	UC_CPU_X86_OPTERON_G2 = 31
+	UC_CPU_X86_OPTERON_G3 = 32
+	UC_CPU_X86_OPTERON_G4 = 33
+	UC_CPU_X86_OPTERON_G5 = 34
+	UC_CPU_X86_EPYC = 35
+	UC_CPU_X86_DHYANA = 36
+	UC_CPU_X86_EPYC_ROME = 37
+
 # X86 registers
 
 	UC_X86_REG_INVALID = 0

bindings/rust/Cargo.toml

@@ -25,3 +25,7 @@ libc = "0.2"
 
 [build-dependencies]
 build-helper = "0.1"
+reqwest = { version = "0.11", features = ["blocking"] }
+flate2 = "1.0.22"
+tar = "0.4.37"
+bytes = "1.1.0"

bindings/rust/build.rs

@@ -1,31 +1,58 @@
-use std::result::Result;
+use bytes::Buf;
+use flate2::read::GzDecoder;
+use reqwest::header::USER_AGENT;
+use std::path::PathBuf;
 use std::{env, process::Command};
+use tar::Archive;
+
+fn find_unicorn(unicorn_dir: &PathBuf) -> Option<PathBuf> {
+    for entry in std::fs::read_dir(unicorn_dir).ok()? {
+        let entry = entry.unwrap();
+        let path = entry.path();
+
+        if path.is_dir() && path.file_name()?.to_str()?.contains("unicorn") {
+            return Some(path);
+        }
+    }
+
+    None
+}
+
+fn download_unicorn() -> Option<String> {
+    // https://docs.github.com/en/rest/reference/repos#download-a-repository-archive-tar
+    let pkg_version;
+    if let Ok(unicorn_version) = env::var("UNICORN_VERSION") {
+        pkg_version = unicorn_version;
+    } else {
+        pkg_version = env::var("CARGO_PKG_VERSION").unwrap();
+    }
+    let out_dir = PathBuf::from(env::var("OUT_DIR").unwrap());
+    let client = reqwest::blocking::Client::new();
+    let resp = client
+        .get(format!(
+            "https://api.github.com/repos/unicorn-engine/unicorn/tarball/{}",
+            pkg_version
+        ))
+        .header(USER_AGENT, "unicorn-engine-rust-bindings")
+        .send()
+        .unwrap()
+        .bytes()
+        .unwrap();
+    let tar = GzDecoder::new(resp.reader());
+
+    let mut archive = Archive::new(tar);
+    archive.unpack(&out_dir).unwrap();
+
+    match find_unicorn(&out_dir) {
+        Some(dir) => Some(String::from(out_dir.join(dir).to_str()?)),
+        None => None,
+    }
+}
 
 fn main() {
-    let out_dir = env::var("OUT_DIR").unwrap();
     let profile = env::var("PROFILE").unwrap();
-    let mut version = String::from("dev");
-    if let Result::Ok(version_env) = env::var("UNICORN_BRANCH") {
-        version = version_env;
-    }
 
-    let unicorn_dir;
-    if let Result::Ok(_) = env::var("CI") {
-        unicorn_dir = format!("../..");
-    } else {
-        unicorn_dir = format!("{}/unicorn_git", out_dir);
-
-        Command::new("rm").arg("-rf").arg(&unicorn_dir);
-
-        Command::new("git")
-            .arg("clone")
-            .arg("git@github.com:unicorn-engine/unicorn.git")
-            .arg("-b")
-            .arg(version)
-            .arg(&unicorn_dir)
-            .output()
-            .expect("Fail to clone Unicorn repository.");
-    }
+    let unicorn_dir = download_unicorn().unwrap();
 
     println!("cargo:rerun-if-changed={}", &unicorn_dir);
 

bindings/rust/tests/unicorn.rs

@@ -1,6 +1,8 @@
 use std::cell::RefCell;
 use std::rc::Rc;
-use unicorn_engine::unicorn_const::{uc_error, Arch, HookType, MemType, Mode, Permission, SECOND_SCALE};
+use unicorn_engine::unicorn_const::{
+    uc_error, Arch, HookType, MemType, Mode, Permission, SECOND_SCALE,
+};
 use unicorn_engine::{InsnSysX86, RegisterARM, RegisterMIPS, RegisterPPC, RegisterX86};
 
 pub static X86_REGISTERS: [RegisterX86; 125] = [
@@ -602,8 +604,8 @@ fn x86_context_save_and_restore() {
         let x86_code: Vec<u8> = vec![
             0x48, 0xB8, 0xEF, 0xBE, 0xAD, 0xDE, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x05,
         ];
-        let mut unicorn =
-            unicorn_engine::Unicorn::new(Arch::X86, mode).expect("failed to initialize unicorn instance");
+        let mut unicorn = unicorn_engine::Unicorn::new(Arch::X86, mode)
+            .expect("failed to initialize unicorn instance");
         let mut emu = unicorn.borrow();
         assert_eq!(emu.mem_map(0x1000, 0x4000, Permission::ALL), Ok(()));
         assert_eq!(emu.mem_write(0x1000, &x86_code), Ok(()));
@@ -619,8 +621,8 @@ fn x86_context_save_and_restore() {
         let context = context.unwrap();
 
         /* and create a new emulator, into which we will "restore" that context */
-        let mut unicorn2 =
-            unicorn_engine::Unicorn::new(Arch::X86, mode).expect("failed to initialize unicorn instance");
+        let mut unicorn2 = unicorn_engine::Unicorn::new(Arch::X86, mode)
+            .expect("failed to initialize unicorn instance");
         let emu2 = unicorn2.borrow();
         assert_eq!(emu2.context_restore(&context), Ok(()));
         for register in X86_REGISTERS.iter() {

format.sh

@@ -0,0 +1,8 @@
+#!/bin/bash
+
+find . -maxdepth 1 "(" -name "*.c" -or -name "*.h" ")" -exec clang-format -i -style=file "{}" ";"
+find ./msvc -maxdepth 1 "(" -name "*.c" -or -name "*.h" ")" -exec clang-format -i -style=file "{}" ";"
+find ./include -maxdepth 2 "(" -name "*.c" -or -name "*.h" ")" -exec clang-format -i -style=file "{}" ";"
+find ./tests/unit -maxdepth 1 "(" -name "*.c" -or -name "*.h" ")" -exec clang-format -i -style=file "{}" ";"
+find ./samples -maxdepth 1 "(" -name "*.c" -or -name "*.h" ")" -exec clang-format -i -style=file "{}" ";"
+find ./qemu "(" -name "unicorn.c" -or -name "unicorn.h" -or -name "unicorn_arm.c" -or -name "unicorn_aarch64.c" ")" -exec clang-format -i -style=file "{}" ";"

glib_compat/gtree.c

@@ -260,7 +260,7 @@ static inline GTreeNode *g_tree_node_next (GTreeNode *node)
     return tmp;
 }
 
-static void g_tree_remove_all (GTree *tree)
+void g_tree_remove_all (GTree *tree)
 {
     GTreeNode *node;
     GTreeNode *next;

glib_compat/gtree.h

@@ -44,6 +44,8 @@ void     g_tree_destroy (GTree *tree);
 
 void     g_tree_insert (GTree *tree, gpointer key, gpointer value);
 
+void g_tree_remove_all (GTree *tree);
+
 gboolean g_tree_remove (GTree *tree, gconstpointer key);
 
 gpointer g_tree_lookup (GTree *tree, gconstpointer key);

include/uc_priv.h

@@ -2,7 +2,6 @@
 /* By Nguyen Anh Quynh <aquynh@gmail.com>, 2015 */
 /* Modified for Unicorn Engine by Chen Huitao<chenhuitao@hfmrit.com>, 2020 */
 
-
 #ifndef UC_PRIV_H
 #define UC_PRIV_H
 
@@ -15,16 +14,22 @@
 
 // These are masks of supported modes for each cpu/arch.
 // They should be updated when changes are made to the uc_mode enum typedef.
-#define UC_MODE_ARM_MASK    (UC_MODE_ARM|UC_MODE_THUMB|UC_MODE_LITTLE_ENDIAN|UC_MODE_MCLASS \
-				|UC_MODE_ARM926|UC_MODE_ARM946|UC_MODE_ARM1176|UC_MODE_BIG_ENDIAN)
-#define UC_MODE_MIPS_MASK   (UC_MODE_MIPS32|UC_MODE_MIPS64|UC_MODE_LITTLE_ENDIAN|UC_MODE_BIG_ENDIAN)
-#define UC_MODE_X86_MASK    (UC_MODE_16|UC_MODE_32|UC_MODE_64|UC_MODE_LITTLE_ENDIAN)
-#define UC_MODE_PPC_MASK    (UC_MODE_PPC32|UC_MODE_PPC64|UC_MODE_BIG_ENDIAN)
-#define UC_MODE_SPARC_MASK  (UC_MODE_SPARC32|UC_MODE_SPARC64|UC_MODE_BIG_ENDIAN)
-#define UC_MODE_M68K_MASK   (UC_MODE_BIG_ENDIAN)
-#define UC_MODE_RISCV_MASK  (UC_MODE_RISCV32|UC_MODE_RISCV64|UC_MODE_LITTLE_ENDIAN)
+#define UC_MODE_ARM_MASK                                                       \
+    (UC_MODE_ARM | UC_MODE_THUMB | UC_MODE_LITTLE_ENDIAN | UC_MODE_MCLASS |    \
+     UC_MODE_ARM926 | UC_MODE_ARM946 | UC_MODE_ARM1176 | UC_MODE_BIG_ENDIAN)
+#define UC_MODE_MIPS_MASK                                                      \
+    (UC_MODE_MIPS32 | UC_MODE_MIPS64 | UC_MODE_LITTLE_ENDIAN |                 \
+     UC_MODE_BIG_ENDIAN)
+#define UC_MODE_X86_MASK                                                       \
+    (UC_MODE_16 | UC_MODE_32 | UC_MODE_64 | UC_MODE_LITTLE_ENDIAN)
+#define UC_MODE_PPC_MASK (UC_MODE_PPC32 | UC_MODE_PPC64 | UC_MODE_BIG_ENDIAN)
+#define UC_MODE_SPARC_MASK                                                     \
+    (UC_MODE_SPARC32 | UC_MODE_SPARC64 | UC_MODE_BIG_ENDIAN)
+#define UC_MODE_M68K_MASK (UC_MODE_BIG_ENDIAN)
+#define UC_MODE_RISCV_MASK                                                     \
+    (UC_MODE_RISCV32 | UC_MODE_RISCV64 | UC_MODE_LITTLE_ENDIAN)
 
-#define ARR_SIZE(a) (sizeof(a)/sizeof(a[0]))
+#define ARR_SIZE(a) (sizeof(a) / sizeof(a[0]))
 
 #define READ_QWORD(x) ((uint64_t)x)
 #define READ_DWORD(x) (x & 0xffffffff)
@@ -36,15 +41,21 @@
 #define WRITE_BYTE_H(x, b) (x = (x & ~0xff00) | ((b & 0xff) << 8))
 #define WRITE_BYTE_L(x, b) (x = (x & ~0xff) | (b & 0xff))
 
+struct TranslationBlock;
 
-typedef uc_err (*query_t)(struct uc_struct *uc, uc_query_type type, size_t *result);
+typedef uc_err (*query_t)(struct uc_struct *uc, uc_query_type type,
+                          size_t *result);
 
 // return 0 on success, -1 on failure
-typedef int (*reg_read_t)(struct uc_struct *uc, unsigned int *regs, void **vals, int count);
-typedef int (*reg_write_t)(struct uc_struct *uc, unsigned int *regs, void *const *vals, int count);
+typedef int (*reg_read_t)(struct uc_struct *uc, unsigned int *regs, void **vals,
+                          int count);
+typedef int (*reg_write_t)(struct uc_struct *uc, unsigned int *regs,
+                           void *const *vals, int count);
 
-typedef int (*context_reg_read_t)(struct uc_context *ctx, unsigned int *regs, void **vals, int count);
-typedef int (*context_reg_write_t)(struct uc_context *ctx, unsigned int *regs, void *const *vals, int count);
+typedef int (*context_reg_read_t)(struct uc_context *ctx, unsigned int *regs,
+                                  void **vals, int count);
+typedef int (*context_reg_write_t)(struct uc_context *ctx, unsigned int *regs,
+                                   void *const *vals, int count);
 typedef struct {
     context_reg_read_t context_reg_read;
     context_reg_write_t context_reg_write;
@@ -52,30 +63,40 @@ typedef struct {
 
 typedef void (*reg_reset_t)(struct uc_struct *uc);
 
-typedef bool (*uc_write_mem_t)(AddressSpace *as, hwaddr addr, const uint8_t *buf, int len);
+typedef bool (*uc_write_mem_t)(AddressSpace *as, hwaddr addr,
+                               const uint8_t *buf, int len);
 
-typedef bool (*uc_read_mem_t)(AddressSpace *as, hwaddr addr, uint8_t *buf, int len);
+typedef bool (*uc_read_mem_t)(AddressSpace *as, hwaddr addr, uint8_t *buf,
+                              int len);
 
-typedef void (*uc_args_void_t)(void*);
+typedef void (*uc_args_void_t)(void *);
 
-typedef void (*uc_args_uc_t)(struct uc_struct*);
-typedef void (*uc_args_int_uc_t)(struct uc_struct*);
+typedef void (*uc_args_uc_t)(struct uc_struct *);
+typedef void (*uc_args_int_uc_t)(struct uc_struct *);
 
-typedef void (*uc_args_uc_long_t)(struct uc_struct*, unsigned long);
+typedef void (*uc_args_uc_long_t)(struct uc_struct *, unsigned long);
 
 typedef void (*uc_args_uc_u64_t)(struct uc_struct *, uint64_t addr);
 
-typedef MemoryRegion* (*uc_args_uc_ram_size_t)(struct uc_struct*,  hwaddr begin, size_t size, uint32_t perms);
+typedef MemoryRegion *(*uc_args_uc_ram_size_t)(struct uc_struct *, hwaddr begin,
+                                               size_t size, uint32_t perms);
 
-typedef MemoryRegion* (*uc_args_uc_ram_size_ptr_t)(struct uc_struct*,  hwaddr begin, size_t size, uint32_t perms, void *ptr);
+typedef MemoryRegion *(*uc_args_uc_ram_size_ptr_t)(struct uc_struct *,
+                                                   hwaddr begin, size_t size,
+                                                   uint32_t perms, void *ptr);
 
-typedef void (*uc_mem_unmap_t)(struct uc_struct*, MemoryRegion *mr);
+typedef void (*uc_mem_unmap_t)(struct uc_struct *, MemoryRegion *mr);
 
 typedef void (*uc_readonly_mem_t)(MemoryRegion *mr, bool readonly);
 
 typedef int (*uc_cpus_init)(struct uc_struct *, const char *);
 
-typedef MemoryRegion* (*uc_memory_map_io_t)(struct uc_struct *uc, ram_addr_t begin, size_t size, uc_cb_mmio_read_t read_cb, uc_cb_mmio_write_t write_cb, void *user_data_read, void *user_data_write);
+typedef MemoryRegion *(*uc_memory_map_io_t)(struct uc_struct *uc,
+                                            ram_addr_t begin, size_t size,
+                                            uc_cb_mmio_read_t read_cb,
+                                            uc_cb_mmio_write_t write_cb,
+                                            void *user_data_read,
+                                            void *user_data_write);
 
 // which interrupt should make emulation stop?
 typedef bool (*uc_args_int_t)(struct uc_struct *uc, int intno);
@@ -84,7 +105,7 @@ typedef bool (*uc_args_int_t)(struct uc_struct *uc, int intno);
 typedef uint64_t (*uc_mem_redirect_t)(uint64_t address);
 
 // validate if Unicorn supports hooking a given instruction
-typedef bool(*uc_insn_hook_validate)(uint32_t insn_enum);
+typedef bool (*uc_insn_hook_validate)(uint32_t insn_enum);
 
 // init target page
 typedef void (*uc_target_page_init)(struct uc_struct *);
@@ -95,12 +116,21 @@ typedef void (*uc_softfloat_initialize)(void);
 // tcg flush softmmu tlb
 typedef void (*uc_tcg_flush_tlb)(struct uc_struct *uc);
 
+// Invalidate the TB at given address
+typedef void (*uc_invalidate_tb_t)(struct uc_struct *uc, uint64_t start,
+                                   size_t len);
+
+// Request generating TB at given address
+typedef uc_err (*uc_gen_tb_t)(struct uc_struct *uc, uint64_t pc, uc_tb *out_tb);
+
 struct hook {
-    int type;            // UC_HOOK_*
-    int insn;            // instruction for HOOK_INSN
-    int refs;            // reference count to free hook stored in multiple lists
-    bool to_delete;      // set to true when the hook is deleted by the user. The destruction of the hook is delayed.
-    uint64_t begin, end; // only trigger if PC or memory access is in this address (depends on hook type)
+    int type;       // UC_HOOK_*
+    int insn;       // instruction for HOOK_INSN
+    int refs;       // reference count to free hook stored in multiple lists
+    bool to_delete; // set to true when the hook is deleted by the user. The
+                    // destruction of the hook is delayed.
+    uint64_t begin, end; // only trigger if PC or memory access is in this
+                         // address (depends on hook type)
     void *callback;      // a uc_cb_* type
     void *user_data;
 };
@@ -127,36 +157,45 @@ typedef enum uc_hook_idx {
     UC_HOOK_MEM_FETCH_IDX,
     UC_HOOK_MEM_READ_AFTER_IDX,
     UC_HOOK_INSN_INVALID_IDX,
+    UC_HOOK_EDGE_GENERATED_IDX,
 
     UC_HOOK_MAX,
 } uc_hook_idx;
 
+// Copy the essential information from TranslationBlock
+#define UC_TB_COPY(uc_tb, tb)                                                  \
+    do {                                                                       \
+        (uc_tb)->pc = tb->pc;                                                  \
+        (uc_tb)->icount = tb->icount;                                          \
+        (uc_tb)->size = tb->size;                                              \
+    } while (0)
+
 // The lowest 6 bits are used for hook type index.
-#define UC_HOOK_IDX_MASK ((1<<6)-1)
+#define UC_HOOK_IDX_MASK ((1 << 6) - 1)
 
 // hook flags
-#define UC_HOOK_FLAG_NO_STOP (1 << 6) // Don't stop emulation in this uc_tracecode.
+#define UC_HOOK_FLAG_NO_STOP                                                   \
+    (1 << 6) // Don't stop emulation in this uc_tracecode.
 
 // The rest of bits are reserved for hook flags.
 #define UC_HOOK_FLAG_MASK (~(UC_HOOK_IDX_MASK))
 
-#define HOOK_FOREACH_VAR_DECLARE                          \
-    struct list_item *cur
+#define HOOK_FOREACH_VAR_DECLARE struct list_item *cur
 
 // for loop macro to loop over hook lists
-#define HOOK_FOREACH(uc, hh, idx)                         \
-    for (                                                 \
-        cur = (uc)->hook[idx##_IDX].head;                 \
-        cur != NULL && ((hh) = (struct hook *)cur->data); \
-        cur = cur->next)
+#define HOOK_FOREACH(uc, hh, idx)                                              \
+    for (cur = (uc)->hook[idx##_IDX].head;                                     \
+         cur != NULL && ((hh) = (struct hook *)cur->data); cur = cur->next)
 
 // if statement to check hook bounds
-#define HOOK_BOUND_CHECK(hh, addr)                  \
-    ((((addr) >= (hh)->begin && (addr) <= (hh)->end) \
-        || (hh)->begin > (hh)->end) && !((hh)->to_delete))
+#define HOOK_BOUND_CHECK(hh, addr)                                             \
+    ((((addr) >= (hh)->begin && (addr) <= (hh)->end) ||                        \
+      (hh)->begin > (hh)->end) &&                                              \
+     !((hh)->to_delete))
 
 #define HOOK_EXISTS(uc, idx) ((uc)->hook[idx##_IDX].head != NULL)
-#define HOOK_EXISTS_BOUNDED(uc, idx, addr) _hook_exists_bounded((uc)->hook[idx##_IDX].head, addr)
+#define HOOK_EXISTS_BOUNDED(uc, idx, addr)                                     \
+    _hook_exists_bounded((uc)->hook[idx##_IDX].head, addr)
 
 static inline bool _hook_exists_bounded(struct list_item *cur, uint64_t addr)
 {
@@ -168,7 +207,7 @@ static inline bool _hook_exists_bounded(struct list_item *cur, uint64_t addr)
     return false;
 }
 
-//relloc increment, KEEP THIS A POWER OF 2!
+// relloc increment, KEEP THIS A POWER OF 2!
 #define MEM_BLOCK_INCR 32
 
 typedef struct TargetPageBits TargetPageBits;
@@ -177,7 +216,7 @@ typedef struct TCGContext TCGContext;
 struct uc_struct {
     uc_arch arch;
     uc_mode mode;
-    uc_err errnum;  // qemu/cpu-exec.c
+    uc_err errnum; // qemu/cpu-exec.c
     AddressSpace address_space_memory;
     AddressSpace address_space_io;
     query_t query;
@@ -187,9 +226,10 @@ struct uc_struct {
 
     uc_write_mem_t write_mem;
     uc_read_mem_t read_mem;
-    uc_args_void_t release;     // release resource when uc_close()
-    uc_args_uc_u64_t set_pc;  // set PC for tracecode
-    uc_args_int_t stop_interrupt;   // check if the interrupt should stop emulation
+    uc_args_void_t release;  // release resource when uc_close()
+    uc_args_uc_u64_t set_pc; // set PC for tracecode
+    uc_args_int_t
+        stop_interrupt; // check if the interrupt should stop emulation
     uc_memory_map_io_t memory_map_io;
 
     uc_args_uc_t init_arch, cpu_exec_init_all;
@@ -204,6 +244,8 @@ struct uc_struct {
     uc_target_page_init target_page;
     uc_softfloat_initialize softfloat_initialize;
     uc_tcg_flush_tlb tcg_flush_tlb;
+    uc_invalidate_tb_t uc_invalidate_tb;
+    uc_gen_tb_t uc_gen_tb;
 
     /*  only 1 cpu in unicorn,
         do not need current_cpu to handle current running cpu. */
@@ -212,21 +254,21 @@ struct uc_struct {
     uc_insn_hook_validate insn_hook_validate;
 
     MemoryRegion *system_memory;    // qemu/exec.c
-    MemoryRegion *system_io;    // qemu/exec.c
+    MemoryRegion *system_io;        // qemu/exec.c
     MemoryRegion io_mem_unassigned; // qemu/exec.c
-    RAMList ram_list;   // qemu/exec.c
+    RAMList ram_list;               // qemu/exec.c
     /* qemu/exec.c */
     unsigned int alloc_hint;
     /* qemu/exec-vary.c */
     TargetPageBits *init_target_page;
-    BounceBuffer bounce;    // qemu/cpu-exec.c
+    BounceBuffer bounce;                // qemu/cpu-exec.c
     volatile sig_atomic_t exit_request; // qemu/cpu-exec.c
     /* qemu/accel/tcg/cpu-exec-common.c */
     /* always be true after call tcg_exec_init(). */
     bool tcg_allowed;
     /* This is a multi-level map on the virtual address space.
        The bottom level has pointers to PageDesc.  */
-    void **l1_map;  // qemu/accel/tcg/translate-all.c
+    void **l1_map; // qemu/accel/tcg/translate-all.c
     size_t l1_map_size;
     /* qemu/accel/tcg/translate-all.c */
     int v_l1_size;
@@ -248,28 +290,34 @@ struct uc_struct {
     uc_hook count_hook;
 
     size_t emu_counter; // current counter of uc_emu_start()
-    size_t emu_count; // save counter of uc_emu_start()
+    size_t emu_count;   // save counter of uc_emu_start()
 
     int size_recur_mem; // size for mem access when in a recursive call
 
-    bool init_tcg;      // already initialized local TCGv variables?
-    bool stop_request;  // request to immediately stop emulation - for uc_emu_stop()
-    bool quit_request;  // request to quit the current TB, but continue to emulate - for uc_mem_protect()
-    bool emulation_done;  // emulation is done by uc_emu_start()
-    bool timed_out;     // emulation timed out, that can retrieve via uc_query(UC_QUERY_TIMEOUT)
-    QemuThread timer;   // timer for emulation timeout
-    uint64_t timeout;   // timeout for uc_emu_start()
+    bool init_tcg;       // already initialized local TCGv variables?
+    bool stop_request;   // request to immediately stop emulation - for
+                         // uc_emu_stop()
+    bool quit_request;   // request to quit the current TB, but continue to
+                         // emulate - for uc_mem_protect()
+    bool emulation_done; // emulation is done by uc_emu_start()
+    bool timed_out;      // emulation timed out, that can retrieve via
+                         // uc_query(UC_QUERY_TIMEOUT)
+    QemuThread timer;    // timer for emulation timeout
+    uint64_t timeout;    // timeout for uc_emu_start()
 
-    uint64_t invalid_addr;  // invalid address to be accessed
-    int invalid_error;  // invalid memory code: 1 = READ, 2 = WRITE, 3 = CODE
+    uint64_t invalid_addr; // invalid address to be accessed
+    int invalid_error;     // invalid memory code: 1 = READ, 2 = WRITE, 3 = CODE
 
-    uint64_t addr_end;  // address where emulation stops (@end param of uc_emu_start())
+    int use_exits;
+    GTree *exits; // addresses where emulation stops (@until param of
+                  // uc_emu_start()) Also see UC_CTL_USE_EXITS for more details.
 
-    int thumb;  // thumb mode for ARM
+    int thumb; // thumb mode for ARM
     MemoryRegion **mapped_blocks;
     uint32_t mapped_block_count;
     uint32_t mapped_block_cache_index;
-    void *qemu_thread_data; // to support cross compile to Windows (qemu-thread-win32.c)
+    void *qemu_thread_data; // to support cross compile to Windows
+                            // (qemu-thread-win32.c)
     uint32_t target_page_size;
     uint32_t target_page_align;
     uint64_t qemu_host_page_size;
@@ -277,26 +325,44 @@ struct uc_struct {
     int qemu_icache_linesize;
     /* ARCH_REGS_STORAGE_SIZE */
     int cpu_context_size;
-    uint64_t next_pc;   // save next PC for some special cases
-    bool hook_insert;	// insert new hook at begin of the hook list (append by default)
-    bool first_tb; // is this the first Translation-Block ever generated since uc_emu_start()?
+    uint64_t next_pc; // save next PC for some special cases
+    bool hook_insert; // insert new hook at begin of the hook list (append by
+                      // default)
+    bool first_tb; // is this the first Translation-Block ever generated since
+                   // uc_emu_start()?
     struct list saved_contexts; // The contexts saved by this uc_struct.
-    bool no_exit_request; // Disable check_exit_request temporarily. A workaround to treat the IT block as a whole block.
+    bool no_exit_request;       // Disable check_exit_request temporarily. A
+                          // workaround to treat the IT block as a whole block.
 };
 
 // Metadata stub for the variable-size cpu context used with uc_context_*()
 // We also save cpu->jmp_env, so emulation can be reentrant
 struct uc_context {
-   size_t context_size;	// size of the real internal context structure
-   size_t jmp_env_size; // size of cpu->jmp_env
-   uc_mode mode; // the mode of this context (uc may be free-ed already)
-   uc_arch arch; // the arch of this context (uc may be free-ed already)
-   struct uc_struct *uc; // the uc_struct which creates this context
-   char data[0]; // context + cpu->jmp_env
+    size_t context_size; // size of the real internal context structure
+    size_t jmp_env_size; // size of cpu->jmp_env
+    uc_mode mode;        // the mode of this context (uc may be free-ed already)
+    uc_arch arch;        // the arch of this context (uc may be free-ed already)
+    struct uc_struct *uc; // the uc_struct which creates this context
+    char data[0];         // context + cpu->jmp_env
 };
 
 // check if this address is mapped in (via uc_mem_map())
-MemoryRegion *memory_mapping(struct uc_struct* uc, uint64_t address);
+MemoryRegion *memory_mapping(struct uc_struct *uc, uint64_t address);
+
+// We have to support 32bit system so we can't hold uint64_t on void*
+static inline void uc_add_exit(uc_engine *uc, uint64_t addr)
+{
+    uint64_t *new_exit = g_malloc(sizeof(uint64_t));
+    *new_exit = addr;
+    g_tree_insert(uc->exits, (gpointer)new_exit, (gpointer)1);
+}
+
+// This function has to exist since we would like to accept uint32_t or
+// it's complex to achieve so.
+static inline int uc_addr_is_exit(uc_engine *uc, uint64_t addr)
+{
+    return g_tree_lookup(uc->exits, (gpointer)(&addr)) == (gpointer)1;
+}
 
 #endif
 /* vim: set ts=4 noet:  */

include/unicorn/arm.h

@@ -12,9 +12,45 @@ extern "C" {
 #endif
 
 #ifdef _MSC_VER
-#pragma warning(disable:4201)
+#pragma warning(disable : 4201)
 #endif
 
+typedef enum uc_cpu_arm {
+    UC_CPU_ARM_926 = 0,
+    UC_CPU_ARM_946,
+    UC_CPU_ARM_1026,
+    UC_CPU_ARM_1136_R2,
+    UC_CPU_ARM_1136,
+    UC_CPU_ARM_1176,
+    UC_CPU_ARM_11MPCORE,
+    UC_CPU_ARM_CORTEX_M0,
+    UC_CPU_ARM_CORTEX_M3,
+    UC_CPU_ARM_CORTEX_M4,
+    UC_CPU_ARM_CORTEX_M7,
+    UC_CPU_ARM_CORTEX_M33,
+    UC_CPU_ARM_CORTEX_R5,
+    UC_CPU_ARM_CORTEX_R5F,
+    UC_CPU_ARM_CORTEX_A8,
+    UC_CPU_ARM_CORTEX_A9,
+    UC_CPU_ARM_CORTEX_A7,
+    UC_CPU_ARM_CORTEX_A15,
+    UC_CPU_ARM_TI925T,
+    UC_CPU_ARM_SA1100,
+    UC_CPU_ARM_SA1110,
+    UC_CPU_ARM_PXA250,
+    UC_CPU_ARM_PXA255,
+    UC_CPU_ARM_PXA260,
+    UC_CPU_ARM_PXA261,
+    UC_CPU_ARM_PXA262,
+    UC_CPU_ARM_PXA270A0,
+    UC_CPU_ARM_PXA270A1,
+    UC_CPU_ARM_PXA270B0,
+    UC_CPU_ARM_PXA270B1,
+    UC_CPU_ARM_PXA270C0,
+    UC_CPU_ARM_PXA270C5,
+    UC_CPU_ARM_MAX
+} uc_cpu_arm;
+
 //> ARM registers
 typedef enum uc_arm_reg {
     UC_ARM_REG_INVALID = 0,
@@ -158,7 +194,7 @@ typedef enum uc_arm_reg {
     UC_ARM_REG_XPSR_NZCVQ,
     UC_ARM_REG_XPSR_G,
     UC_ARM_REG_XPSR_NZCVQG,
-    UC_ARM_REG_ENDING,		// <-- mark the end of the list or registers
+    UC_ARM_REG_ENDING, // <-- mark the end of the list or registers
 
     //> alias registers
     UC_ARM_REG_R13 = UC_ARM_REG_SP,

include/unicorn/arm64.h

@@ -12,9 +12,16 @@ extern "C" {
 #endif
 
 #ifdef _MSC_VER
-#pragma warning(disable:4201)
+#pragma warning(disable : 4201)
 #endif
 
+typedef enum uc_cpu_aarch64 {
+    UC_CPU_AARCH64_A57 = 0,
+    UC_CPU_AARCH64_A53,
+    UC_CPU_AARCH64_A72,
+    UC_CPU_AARCH64_MAX
+} uc_cpu_aarch64;
+
 //> ARM64 registers
 typedef enum uc_arm64_reg {
     UC_ARM64_REG_INVALID = 0,
@@ -281,7 +288,7 @@ typedef enum uc_arm64_reg {
     UC_ARM64_REG_V31,
 
     //> pseudo registers
-    UC_ARM64_REG_PC,			// program counter register
+    UC_ARM64_REG_PC, // program counter register
 
     UC_ARM64_REG_CPACR_EL1,
 
@@ -327,7 +334,7 @@ typedef enum uc_arm64_reg {
     UC_ARM64_REG_VBAR_EL2,
     UC_ARM64_REG_VBAR_EL3,
 
-    UC_ARM64_REG_ENDING,		// <-- mark the end of the list of registers
+    UC_ARM64_REG_ENDING, // <-- mark the end of the list of registers
 
     //> alias registers
 

include/unicorn/m68k.h

@@ -12,9 +12,21 @@ extern "C" {
 #endif
 
 #ifdef _MSC_VER
-#pragma warning(disable:4201)
+#pragma warning(disable : 4201)
 #endif
 
+typedef enum uc_cpu_m68k {
+    UC_CPU_M5206_CPU = 0,
+    UC_CPU_M68000_CPU,
+    UC_CPU_M68020_CPU,
+    UC_CPU_M68030_CPU,
+    UC_CPU_M68040_CPU,
+    UC_CPU_M68060_CPU,
+    UC_CPU_M5208_CPU,
+    UC_CPU_CFV4E_CPU,
+    UC_CPU_ANY_CPU,
+} uc_cpu_m68k;
+
 //> M68K registers
 typedef enum uc_m68k_reg {
     UC_M68K_REG_INVALID = 0,
@@ -40,7 +52,7 @@ typedef enum uc_m68k_reg {
     UC_M68K_REG_SR,
     UC_M68K_REG_PC,
 
-    UC_M68K_REG_ENDING,   // <-- mark the end of the list of registers
+    UC_M68K_REG_ENDING, // <-- mark the end of the list of registers
 } uc_m68k_reg;
 
 #ifdef __cplusplus

include/unicorn/mips.h

@@ -16,9 +16,41 @@ extern "C" {
 #undef mips
 
 #ifdef _MSC_VER
-#pragma warning(disable:4201)
+#pragma warning(disable : 4201)
 #endif
 
+typedef enum uc_cpu_mips {
+    UC_CPU_MIPS_4KC = 0,
+    UC_CPU_MIPS_4KM,
+    UC_CPU_MIPS_4KECR1,
+    UC_CPU_MIPS_4KEMR1,
+    UC_CPU_MIPS_4KEC,
+    UC_CPU_MIPS_4KEM,
+    UC_CPU_MIPS_24KC,
+    UC_CPU_MIPS_24KEC,
+    UC_CPU_MIPS_24KF,
+    UC_CPU_MIPS_34KF,
+    UC_CPU_MIPS_74KF,
+    UC_CPU_MIPS_M14K,
+    UC_CPU_MIPS_M14KC,
+    UC_CPU_MIPS_P5600,
+    UC_CPU_MIPS_MIPS32R6_GENERIC,
+    UC_CPU_MIPS_I7200,
+    UC_CPU_MIPS_R4000,
+    UC_CPU_MIPS_VR5432,
+    UC_CPU_MIPS_5KC,
+    UC_CPU_MIPS_5KF,
+    UC_CPU_MIPS_20KC,
+    UC_CPU_MIPS_MIPS64R2_GENERIC,
+    UC_CPU_MIPS_5KEC,
+    UC_CPU_MIPS_5KEF,
+    UC_CPU_MIPS_I6400,
+    UC_CPU_MIPS_I6500,
+    UC_CPU_MIPS_LOONGSON_2E,
+    UC_CPU_MIPS_LOONGSON_2F,
+    UC_CPU_MIPS_MIPS64DSPR2
+} uc_cpu_mips;
+
 //> MIPS registers
 typedef enum UC_MIPS_REG {
     UC_MIPS_REG_INVALID = 0,
@@ -179,7 +211,7 @@ typedef enum UC_MIPS_REG {
     UC_MIPS_REG_CP0_USERLOCAL,
     UC_MIPS_REG_CP0_STATUS,
 
-    UC_MIPS_REG_ENDING,	// <-- mark the end of the list or registers
+    UC_MIPS_REG_ENDING, // <-- mark the end of the list or registers
 
     // alias registers
     UC_MIPS_REG_ZERO = UC_MIPS_REG_0,
@@ -212,7 +244,8 @@ typedef enum UC_MIPS_REG {
     UC_MIPS_REG_K1 = UC_MIPS_REG_27,
     UC_MIPS_REG_GP = UC_MIPS_REG_28,
     UC_MIPS_REG_SP = UC_MIPS_REG_29,
-    UC_MIPS_REG_FP = UC_MIPS_REG_30, UC_MIPS_REG_S8 = UC_MIPS_REG_30,
+    UC_MIPS_REG_FP = UC_MIPS_REG_30,
+    UC_MIPS_REG_S8 = UC_MIPS_REG_30,
     UC_MIPS_REG_RA = UC_MIPS_REG_31,
 
     UC_MIPS_REG_HI0 = UC_MIPS_REG_AC0,

include/unicorn/platform.h

@@ -22,16 +22,17 @@ MSVC++ 7.0  _MSC_VER == 1300
 MSVC++ 6.0  _MSC_VER == 1200
 MSVC++ 5.0  _MSC_VER == 1100
 */
-#define MSC_VER_VS2003	1310
-#define MSC_VER_VS2005	1400
-#define MSC_VER_VS2008	1500
-#define MSC_VER_VS2010	1600
-#define MSC_VER_VS2012	1700
-#define MSC_VER_VS2013	1800
-#define MSC_VER_VS2015	1900
+#define MSC_VER_VS2003 1310
+#define MSC_VER_VS2005 1400
+#define MSC_VER_VS2008 1500
+#define MSC_VER_VS2010 1600
+#define MSC_VER_VS2012 1700
+#define MSC_VER_VS2013 1800
+#define MSC_VER_VS2015 1900
 
 // handle stdbool.h compatibility
-#if !defined(__CYGWIN__) && !defined(__MINGW32__) && !defined(__MINGW64__) && (defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64))
+#if !defined(__CYGWIN__) && !defined(__MINGW32__) && !defined(__MINGW64__) &&  \
+    (defined(WIN32) || defined(WIN64) || defined(_WIN32) || defined(_WIN64))
 // MSVC
 
 // stdbool.h
@@ -41,36 +42,38 @@ MSVC++ 5.0  _MSC_VER == 1100
 typedef unsigned char bool;
 #define false 0
 #define true 1
-#endif  // __cplusplus
+#endif // __cplusplus
 
 #else
 // VisualStudio 2013+ -> C99 is supported
 #include <stdbool.h>
-#endif  // (_MSC_VER < MSC_VER_VS2013) || defined(_KERNEL_MODE)
+#endif // (_MSC_VER < MSC_VER_VS2013) || defined(_KERNEL_MODE)
 
 #else
 // not MSVC -> C99 is supported
 #include <stdbool.h>
-#endif  // !defined(__CYGWIN__) && !defined(__MINGW32__) && !defined(__MINGW64__) && (defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64))
+#endif // !defined(__CYGWIN__) && !defined(__MINGW32__) && !defined(__MINGW64__)
+       // && (defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined
+       // (_WIN64))
 
 #if (defined(_MSC_VER) && (_MSC_VER < MSC_VER_VS2010)) || defined(_KERNEL_MODE)
 // this system does not have stdint.h
-typedef signed char  int8_t;
+typedef signed char int8_t;
 typedef signed short int16_t;
-typedef signed int   int32_t;
-typedef unsigned char  uint8_t;
+typedef signed int int32_t;
+typedef unsigned char uint8_t;
 typedef unsigned short uint16_t;
-typedef unsigned int   uint32_t;
-typedef signed long long   int64_t;
+typedef unsigned int uint32_t;
+typedef signed long long int64_t;
 typedef unsigned long long uint64_t;
 
-typedef signed char        int_fast8_t;
-typedef int                int_fast16_t;
-typedef int                int_fast32_t;
-typedef long long          int_fast64_t;
-typedef unsigned char      uint_fast8_t;
-typedef unsigned int       uint_fast16_t;
-typedef unsigned int       uint_fast32_t;
+typedef signed char int_fast8_t;
+typedef int int_fast16_t;
+typedef int int_fast32_t;
+typedef long long int_fast64_t;
+typedef unsigned char uint_fast8_t;
+typedef unsigned int uint_fast16_t;
+typedef unsigned int uint_fast32_t;
 typedef unsigned long long uint_fast64_t;
 
 #if !defined(_W64)
@@ -82,57 +85,57 @@ typedef unsigned long long uint_fast64_t;
 #endif
 
 #ifndef _INTPTR_T_DEFINED
- #define _INTPTR_T_DEFINED
- #ifdef _WIN64
-typedef long long          intptr_t;
- #else /* _WIN64 */
-typedef _W64 int           intptr_t;
- #endif /* _WIN64 */
+#define _INTPTR_T_DEFINED
+#ifdef _WIN64
+typedef long long intptr_t;
+#else  /* _WIN64 */
+typedef _W64 int intptr_t;
+#endif /* _WIN64 */
 #endif /* _INTPTR_T_DEFINED */
 
 #ifndef _UINTPTR_T_DEFINED
- #define _UINTPTR_T_DEFINED
- #ifdef _WIN64
+#define _UINTPTR_T_DEFINED
+#ifdef _WIN64
 typedef unsigned long long uintptr_t;
- #else /* _WIN64 */
-typedef _W64 unsigned int  uintptr_t;
- #endif /* _WIN64 */
+#else  /* _WIN64 */
+typedef _W64 unsigned int uintptr_t;
+#endif /* _WIN64 */
 #endif /* _UINTPTR_T_DEFINED */
 
-#define INT8_MIN         (-127i8 - 1)
-#define INT16_MIN        (-32767i16 - 1)
-#define INT32_MIN        (-2147483647i32 - 1)
-#define INT64_MIN        (-9223372036854775807i64 - 1)
-#define INT8_MAX         127i8
-#define INT16_MAX        32767i16
-#define INT32_MAX        2147483647i32
-#define INT64_MAX        9223372036854775807i64
-#define UINT8_MAX        0xffui8
-#define UINT16_MAX       0xffffui16
-#define UINT32_MAX       0xffffffffui32
-#define UINT64_MAX       0xffffffffffffffffui64
+#define INT8_MIN (-127i8 - 1)
+#define INT16_MIN (-32767i16 - 1)
+#define INT32_MIN (-2147483647i32 - 1)
+#define INT64_MIN (-9223372036854775807i64 - 1)
+#define INT8_MAX 127i8
+#define INT16_MAX 32767i16
+#define INT32_MAX 2147483647i32
+#define INT64_MAX 9223372036854775807i64
+#define UINT8_MAX 0xffui8
+#define UINT16_MAX 0xffffui16
+#define UINT32_MAX 0xffffffffui32
+#define UINT64_MAX 0xffffffffffffffffui64
 
-#define INT_FAST8_MIN    INT8_MIN
-#define INT_FAST16_MIN   INT32_MIN
-#define INT_FAST32_MIN   INT32_MIN
-#define INT_FAST64_MIN   INT64_MIN
-#define INT_FAST8_MAX    INT8_MAX
-#define INT_FAST16_MAX   INT32_MAX
-#define INT_FAST32_MAX   INT32_MAX
-#define INT_FAST64_MAX   INT64_MAX
-#define UINT_FAST8_MAX   UINT8_MAX
-#define UINT_FAST16_MAX  UINT32_MAX
-#define UINT_FAST32_MAX  UINT32_MAX
-#define UINT_FAST64_MAX  UINT64_MAX
+#define INT_FAST8_MIN INT8_MIN
+#define INT_FAST16_MIN INT32_MIN
+#define INT_FAST32_MIN INT32_MIN
+#define INT_FAST64_MIN INT64_MIN
+#define INT_FAST8_MAX INT8_MAX
+#define INT_FAST16_MAX INT32_MAX
+#define INT_FAST32_MAX INT32_MAX
+#define INT_FAST64_MAX INT64_MAX
+#define UINT_FAST8_MAX UINT8_MAX
+#define UINT_FAST16_MAX UINT32_MAX
+#define UINT_FAST32_MAX UINT32_MAX
+#define UINT_FAST64_MAX UINT64_MAX
 
 #ifdef _WIN64
-#define INTPTR_MIN      INT64_MIN
-#define INTPTR_MAX      INT64_MAX
-#define UINTPTR_MAX     UINT64_MAX
+#define INTPTR_MIN INT64_MIN
+#define INTPTR_MAX INT64_MAX
+#define UINTPTR_MAX UINT64_MAX
 #else /* _WIN64 */
-#define INTPTR_MIN      INT32_MIN
-#define INTPTR_MAX      INT32_MAX
-#define UINTPTR_MAX     UINT32_MAX
+#define INTPTR_MIN INT32_MIN
+#define INTPTR_MAX INT32_MAX
+#define UINTPTR_MAX UINT32_MAX
 #endif /* _WIN64 */
 
 #else // this system has stdint.h
@@ -142,7 +145,8 @@ typedef _W64 unsigned int  uintptr_t;
 #endif
 
 #include <stdint.h>
-#endif  // (defined(_MSC_VER) && (_MSC_VER < MSC_VER_VS2010)) || defined(_KERNEL_MODE)
+#endif // (defined(_MSC_VER) && (_MSC_VER < MSC_VER_VS2010)) ||
+       // defined(_KERNEL_MODE)
 
 // handle inttypes.h compatibility
 #if (defined(_MSC_VER) && (_MSC_VER < MSC_VER_VS2013)) || defined(_KERNEL_MODE)
@@ -151,52 +155,53 @@ typedef _W64 unsigned int  uintptr_t;
 #define __PRI_8_LENGTH_MODIFIER__ "hh"
 #define __PRI_64_LENGTH_MODIFIER__ "ll"
 
-#define PRId8         __PRI_8_LENGTH_MODIFIER__ "d"
-#define PRIi8         __PRI_8_LENGTH_MODIFIER__ "i"
-#define PRIo8         __PRI_8_LENGTH_MODIFIER__ "o"
-#define PRIu8         __PRI_8_LENGTH_MODIFIER__ "u"
-#define PRIx8         __PRI_8_LENGTH_MODIFIER__ "x"
-#define PRIX8         __PRI_8_LENGTH_MODIFIER__ "X"
+#define PRId8 __PRI_8_LENGTH_MODIFIER__ "d"
+#define PRIi8 __PRI_8_LENGTH_MODIFIER__ "i"
+#define PRIo8 __PRI_8_LENGTH_MODIFIER__ "o"
+#define PRIu8 __PRI_8_LENGTH_MODIFIER__ "u"
+#define PRIx8 __PRI_8_LENGTH_MODIFIER__ "x"
+#define PRIX8 __PRI_8_LENGTH_MODIFIER__ "X"
 
-#define PRId16        "hd"
-#define PRIi16        "hi"
-#define PRIo16        "ho"
-#define PRIu16        "hu"
-#define PRIx16        "hx"
-#define PRIX16        "hX"
+#define PRId16 "hd"
+#define PRIi16 "hi"
+#define PRIo16 "ho"
+#define PRIu16 "hu"
+#define PRIx16 "hx"
+#define PRIX16 "hX"
 
 #if defined(_MSC_VER) && (_MSC_VER <= MSC_VER_VS2012)
-#define PRId32        "ld"
-#define PRIi32        "li"
-#define PRIo32        "lo"
-#define PRIu32        "lu"
-#define PRIx32        "lx"
-#define PRIX32        "lX"
-#else	// OSX
-#define PRId32        "d"
-#define PRIi32        "i"
-#define PRIo32        "o"
-#define PRIu32        "u"
-#define PRIx32        "x"
-#define PRIX32        "X"
-#endif  // defined(_MSC_VER) && (_MSC_VER <= MSC_VER_VS2012)
+#define PRId32 "ld"
+#define PRIi32 "li"
+#define PRIo32 "lo"
+#define PRIu32 "lu"
+#define PRIx32 "lx"
+#define PRIX32 "lX"
+#else // OSX
+#define PRId32 "d"
+#define PRIi32 "i"
+#define PRIo32 "o"
+#define PRIu32 "u"
+#define PRIx32 "x"
+#define PRIX32 "X"
+#endif // defined(_MSC_VER) && (_MSC_VER <= MSC_VER_VS2012)
 
 #if defined(_MSC_VER) && (_MSC_VER <= MSC_VER_VS2012)
 // redefine functions from inttypes.h used in cstool
 #define strtoull _strtoui64
 #endif
 
-#define PRId64        __PRI_64_LENGTH_MODIFIER__ "d"
-#define PRIi64        __PRI_64_LENGTH_MODIFIER__ "i"
-#define PRIo64        __PRI_64_LENGTH_MODIFIER__ "o"
-#define PRIu64        __PRI_64_LENGTH_MODIFIER__ "u"
-#define PRIx64        __PRI_64_LENGTH_MODIFIER__ "x"
-#define PRIX64        __PRI_64_LENGTH_MODIFIER__ "X"
+#define PRId64 __PRI_64_LENGTH_MODIFIER__ "d"
+#define PRIi64 __PRI_64_LENGTH_MODIFIER__ "i"
+#define PRIo64 __PRI_64_LENGTH_MODIFIER__ "o"
+#define PRIu64 __PRI_64_LENGTH_MODIFIER__ "u"
+#define PRIx64 __PRI_64_LENGTH_MODIFIER__ "x"
+#define PRIX64 __PRI_64_LENGTH_MODIFIER__ "X"
 
 #else
 // this system has inttypes.h by default
 #include <inttypes.h>
-#endif // #if defined(_MSC_VER) && (_MSC_VER < MSC_VER_VS2013) || defined(_KERNEL_MODE)
+#endif // #if defined(_MSC_VER) && (_MSC_VER < MSC_VER_VS2013) ||
+       // defined(_KERNEL_MODE)
 
 // sys/time.h compatibility
 #if defined(_MSC_VER)
@@ -220,7 +225,7 @@ static int usleep(uint32_t usec)
     if (!timer)
         return -1;
 
-    due.QuadPart = (-((int64_t) usec)) * 10LL;
+    due.QuadPart = (-((int64_t)usec)) * 10LL;
     if (!SetWaitableTimer(timer, &due, 0, NULL, NULL, 0)) {
         CloseHandle(timer);
         return -1;
@@ -237,23 +242,22 @@ static int usleep(uint32_t usec)
 
 // misc support
 #if defined(_MSC_VER)
-#ifdef  _WIN64
-typedef signed __int64    ssize_t;
+#ifdef _WIN64
+typedef signed __int64 ssize_t;
 #else
-typedef _W64 signed int   ssize_t;
+typedef _W64 signed int ssize_t;
 #endif
 
 #ifndef va_copy
-#define va_copy(d,s) ((d) = (s))
+#define va_copy(d, s) ((d) = (s))
 #endif
-#define strcasecmp	_stricmp
+#define strcasecmp _stricmp
 #if (_MSC_VER < MSC_VER_VS2015)
-#define snprintf	_snprintf
+#define snprintf _snprintf
 #endif
 #if (_MSC_VER <= MSC_VER_VS2013)
-#define strtoll		_strtoi64
+#define strtoll _strtoi64
 #endif
 #endif
 
-
 #endif // UNICORN_PLATFORM_H

include/unicorn/ppc.h

@@ -12,9 +12,314 @@ extern "C" {
 #endif
 
 #ifdef _MSC_VER
-#pragma warning(disable:4201)
+#pragma warning(disable : 4201)
 #endif
 
+typedef enum uc_cpu_ppc {
+    UC_CPU_PPC_401A1 = 0,
+    UC_CPU_PPC_401B2,
+    UC_CPU_PPC_401C2,
+    UC_CPU_PPC_401D2,
+    UC_CPU_PPC_401E2,
+    UC_CPU_PPC_401F2,
+    UC_CPU_PPC_401G2,
+    UC_CPU_PPC_COBRA,
+    UC_CPU_PPC_403GA,
+    UC_CPU_PPC_403GB,
+    UC_CPU_PPC_403GC,
+    UC_CPU_PPC_403GCX,
+    UC_CPU_PPC_405D2,
+    UC_CPU_PPC_405D4,
+    UC_CPU_PPC_405CRA,
+    UC_CPU_PPC_405CRB,
+    UC_CPU_PPC_405CRC,
+    UC_CPU_PPC_405EP,
+    UC_CPU_PPC_405EZ,
+    UC_CPU_PPC_405GPA,
+    UC_CPU_PPC_405GPB,
+    UC_CPU_PPC_405GPC,
+    UC_CPU_PPC_405GPD,
+    UC_CPU_PPC_405GPR,
+    UC_CPU_PPC_405LP,
+    UC_CPU_PPC_NPE405H,
+    UC_CPU_PPC_NPE405H2,
+    UC_CPU_PPC_NPE405L,
+    UC_CPU_PPC_NPE4GS3,
+    UC_CPU_PPC_STB03,
+    UC_CPU_PPC_STB04,
+    UC_CPU_PPC_STB25,
+    UC_CPU_PPC_X2VP4,
+    UC_CPU_PPC_440_XILINX,
+    UC_CPU_PPC_440EPA,
+    UC_CPU_PPC_440EPB,
+    UC_CPU_PPC_440GPB,
+    UC_CPU_PPC_440GPC,
+    UC_CPU_PPC_440GRX,
+    UC_CPU_PPC_440GXA,
+    UC_CPU_PPC_440GXB,
+    UC_CPU_PPC_440GXC,
+    UC_CPU_PPC_440GXF,
+    UC_CPU_PPC_440SP,
+    UC_CPU_PPC_440SP2,
+    UC_CPU_PPC_440SPE,
+    UC_CPU_PPC_460EXB,
+    UC_CPU_PPC_MPC5XX,
+    UC_CPU_PPC_MPC8XX,
+    UC_CPU_PPC_G2,
+    UC_CPU_PPC_G2H4,
+    UC_CPU_PPC_G2GP,
+    UC_CPU_PPC_G2LS,
+    UC_CPU_PPC_MPC603,
+    UC_CPU_PPC_G2_HIP3,
+    UC_CPU_PPC_G2_HIP4,
+    UC_CPU_PPC_G2LE,
+    UC_CPU_PPC_G2LEGP,
+    UC_CPU_PPC_G2LELS,
+    UC_CPU_PPC_G2LEGP1,
+    UC_CPU_PPC_G2LEGP3,
+    UC_CPU_PPC_E200Z5,
+    UC_CPU_PPC_E200Z6,
+    UC_CPU_PPC_E300C1,
+    UC_CPU_PPC_E300C2,
+    UC_CPU_PPC_E300C3,
+    UC_CPU_PPC_E300C4,
+    UC_CPU_PPC_E500V1_V10,
+    UC_CPU_PPC_E500V1_V20,
+    UC_CPU_PPC_E500V2_V10,
+    UC_CPU_PPC_E500V2_V11,
+    UC_CPU_PPC_E500V2_V20,
+    UC_CPU_PPC_E500V2_V21,
+    UC_CPU_PPC_E500V2_V22,
+    UC_CPU_PPC_E500V2_V30,
+    UC_CPU_PPC_E500MC,
+    UC_CPU_PPC_E5500,
+    UC_CPU_PPC_E6500,
+    UC_CPU_PPC_E600,
+    UC_CPU_PPC_601_V0,
+    UC_CPU_PPC_601_V1,
+    UC_CPU_PPC_601_V2,
+    UC_CPU_PPC_602,
+    UC_CPU_PPC_603,
+    UC_CPU_PPC_603E_V11,
+    UC_CPU_PPC_603E_V12,
+    UC_CPU_PPC_603E_V13,
+    UC_CPU_PPC_603E_V14,
+    UC_CPU_PPC_603E_V22,
+    UC_CPU_PPC_603E_V3,
+    UC_CPU_PPC_603E_V4,
+    UC_CPU_PPC_603E_V41,
+    UC_CPU_PPC_603E7T,
+    UC_CPU_PPC_603E7V,
+    UC_CPU_PPC_603E7V1,
+    UC_CPU_PPC_603E7V2,
+    UC_CPU_PPC_603E7,
+    UC_CPU_PPC_603P,
+    UC_CPU_PPC_604,
+    UC_CPU_PPC_604E_V10,
+    UC_CPU_PPC_604E_V22,
+    UC_CPU_PPC_604E_V24,
+    UC_CPU_PPC_604R,
+    UC_CPU_PPC_7X0_V10,
+    UC_CPU_PPC_7X0_V20,
+    UC_CPU_PPC_7X0_V21,
+    UC_CPU_PPC_7X0_V22,
+    UC_CPU_PPC_7X0_V30,
+    UC_CPU_PPC_7X0_V31,
+    UC_CPU_PPC_740E,
+    UC_CPU_PPC_750E,
+    UC_CPU_PPC_7X0P,
+    UC_CPU_PPC_750CL_V10,
+    UC_CPU_PPC_750CL_V20,
+    UC_CPU_PPC_750CX_V10,
+    UC_CPU_PPC_750CX_V20,
+    UC_CPU_PPC_750CX_V21,
+    UC_CPU_PPC_750CX_V22,
+    UC_CPU_PPC_750CXE_V21,
+    UC_CPU_PPC_750CXE_V22,
+    UC_CPU_PPC_750CXE_V23,
+    UC_CPU_PPC_750CXE_V24,
+    UC_CPU_PPC_750CXE_V24B,
+    UC_CPU_PPC_750CXE_V30,
+    UC_CPU_PPC_750CXE_V31,
+    UC_CPU_PPC_750CXE_V31B,
+    UC_CPU_PPC_750CXR,
+    UC_CPU_PPC_750FL,
+    UC_CPU_PPC_750FX_V10,
+    UC_CPU_PPC_750FX_V20,
+    UC_CPU_PPC_750FX_V21,
+    UC_CPU_PPC_750FX_V22,
+    UC_CPU_PPC_750FX_V23,
+    UC_CPU_PPC_750GL,
+    UC_CPU_PPC_750GX_V10,
+    UC_CPU_PPC_750GX_V11,
+    UC_CPU_PPC_750GX_V12,
+    UC_CPU_PPC_750L_V20,
+    UC_CPU_PPC_750L_V21,
+    UC_CPU_PPC_750L_V22,
+    UC_CPU_PPC_750L_V30,
+    UC_CPU_PPC_750L_V32,
+    UC_CPU_PPC_7X5_V10,
+    UC_CPU_PPC_7X5_V11,
+    UC_CPU_PPC_7X5_V20,
+    UC_CPU_PPC_7X5_V21,
+    UC_CPU_PPC_7X5_V22,
+    UC_CPU_PPC_7X5_V23,
+    UC_CPU_PPC_7X5_V24,
+    UC_CPU_PPC_7X5_V25,
+    UC_CPU_PPC_7X5_V26,
+    UC_CPU_PPC_7X5_V27,
+    UC_CPU_PPC_7X5_V28,
+    UC_CPU_PPC_7400_V10,
+    UC_CPU_PPC_7400_V11,
+    UC_CPU_PPC_7400_V20,
+    UC_CPU_PPC_7400_V21,
+    UC_CPU_PPC_7400_V22,
+    UC_CPU_PPC_7400_V26,
+    UC_CPU_PPC_7400_V27,
+    UC_CPU_PPC_7400_V28,
+    UC_CPU_PPC_7400_V29,
+    UC_CPU_PPC_7410_V10,
+    UC_CPU_PPC_7410_V11,
+    UC_CPU_PPC_7410_V12,
+    UC_CPU_PPC_7410_V13,
+    UC_CPU_PPC_7410_V14,
+    UC_CPU_PPC_7448_V10,
+    UC_CPU_PPC_7448_V11,
+    UC_CPU_PPC_7448_V20,
+    UC_CPU_PPC_7448_V21,
+    UC_CPU_PPC_7450_V10,
+    UC_CPU_PPC_7450_V11,
+    UC_CPU_PPC_7450_V12,
+    UC_CPU_PPC_7450_V20,
+    UC_CPU_PPC_7450_V21,
+    UC_CPU_PPC_74X1_V23,
+    UC_CPU_PPC_74X1_V210,
+    UC_CPU_PPC_74X5_V10,
+    UC_CPU_PPC_74X5_V21,
+    UC_CPU_PPC_74X5_V32,
+    UC_CPU_PPC_74X5_V33,
+    UC_CPU_PPC_74X5_V34,
+    UC_CPU_PPC_74X7_V10,
+    UC_CPU_PPC_74X7_V11,
+    UC_CPU_PPC_74X7_V12,
+    UC_CPU_PPC_74X7A_V10,
+    UC_CPU_PPC_74X7A_V11,
+    UC_CPU_PPC_74X7A_V12,
+    UC_CPU_PPC_IOP480 = UC_CPU_PPC_401B2,
+    UC_CPU_PPC_X2VP20 = UC_CPU_PPC_440GXF,
+    UC_CPU_PPC_440GRA = UC_CPU_PPC_440EPB,
+    UC_CPU_PPC_440EPX = UC_CPU_PPC_440GRX,
+    UC_CPU_PPC_MPC5200_V10 = UC_CPU_PPC_G2LEGP1,
+    UC_CPU_PPC_MPC5200_V11 = UC_CPU_PPC_G2LEGP1,
+    UC_CPU_PPC_MPC5200_V12 = UC_CPU_PPC_G2LEGP1,
+    UC_CPU_PPC_MPC5200B_V20 = UC_CPU_PPC_G2LEGP1,
+    UC_CPU_PPC_MPC5200B_V21 = UC_CPU_PPC_G2LEGP1,
+    UC_CPU_PPC_MPC834X = UC_CPU_PPC_E300C1,
+    UC_CPU_PPC_MPC837X = UC_CPU_PPC_E300C4,
+    UC_CPU_PPC_E500 = UC_CPU_PPC_E500V2_V22,
+    UC_CPU_PPC_MPC8533_V10 = UC_CPU_PPC_E500V2_V21,
+    UC_CPU_PPC_MPC8533_V11 = UC_CPU_PPC_E500V2_V22,
+    UC_CPU_PPC_MPC8533E_V10 = UC_CPU_PPC_E500V2_V21,
+    UC_CPU_PPC_MPC8533E_V11 = UC_CPU_PPC_E500V2_V22,
+    UC_CPU_PPC_MPC8540_V10 = UC_CPU_PPC_E500V1_V10,
+    UC_CPU_PPC_MPC8540_V20 = UC_CPU_PPC_E500V1_V20,
+    UC_CPU_PPC_MPC8540_V21 = UC_CPU_PPC_E500V1_V20,
+    UC_CPU_PPC_MPC8541_V10 = UC_CPU_PPC_E500V1_V20,
+    UC_CPU_PPC_MPC8541_V11 = UC_CPU_PPC_E500V1_V20,
+    UC_CPU_PPC_MPC8541E_V10 = UC_CPU_PPC_E500V1_V20,
+    UC_CPU_PPC_MPC8541E_V11 = UC_CPU_PPC_E500V1_V20,
+    UC_CPU_PPC_MPC8543_V10 = UC_CPU_PPC_E500V2_V10,
+    UC_CPU_PPC_MPC8543_V11 = UC_CPU_PPC_E500V2_V11,
+    UC_CPU_PPC_MPC8543_V20 = UC_CPU_PPC_E500V2_V20,
+    UC_CPU_PPC_MPC8543_V21 = UC_CPU_PPC_E500V2_V21,
+    UC_CPU_PPC_MPC8543E_V10 = UC_CPU_PPC_E500V2_V10,
+    UC_CPU_PPC_MPC8543E_V11 = UC_CPU_PPC_E500V2_V11,
+    UC_CPU_PPC_MPC8543E_V20 = UC_CPU_PPC_E500V2_V20,
+    UC_CPU_PPC_MPC8543E_V21 = UC_CPU_PPC_E500V2_V21,
+    UC_CPU_PPC_MPC8544_V10 = UC_CPU_PPC_E500V2_V21,
+    UC_CPU_PPC_MPC8544_V11 = UC_CPU_PPC_E500V2_V22,
+    UC_CPU_PPC_MPC8544E_V11 = UC_CPU_PPC_E500V2_V22,
+    UC_CPU_PPC_MPC8544E_V10 = UC_CPU_PPC_E500V2_V21,
+    UC_CPU_PPC_MPC8545_V10 = UC_CPU_PPC_E500V2_V10,
+    UC_CPU_PPC_MPC8545_V20 = UC_CPU_PPC_E500V2_V20,
+    UC_CPU_PPC_MPC8545_V21 = UC_CPU_PPC_E500V2_V21,
+    UC_CPU_PPC_MPC8545E_V10 = UC_CPU_PPC_E500V2_V10,
+    UC_CPU_PPC_MPC8545E_V20 = UC_CPU_PPC_E500V2_V20,
+    UC_CPU_PPC_MPC8545E_V21 = UC_CPU_PPC_E500V2_V21,
+    UC_CPU_PPC_MPC8547E_V10 = UC_CPU_PPC_E500V2_V10,
+    UC_CPU_PPC_MPC8547E_V20 = UC_CPU_PPC_E500V2_V20,
+    UC_CPU_PPC_MPC8547E_V21 = UC_CPU_PPC_E500V2_V21,
+    UC_CPU_PPC_MPC8548_V10 = UC_CPU_PPC_E500V2_V10,
+    UC_CPU_PPC_MPC8548_V11 = UC_CPU_PPC_E500V2_V11,
+    UC_CPU_PPC_MPC8548_V20 = UC_CPU_PPC_E500V2_V20,
+    UC_CPU_PPC_MPC8548_V21 = UC_CPU_PPC_E500V2_V21,
+    UC_CPU_PPC_MPC8548E_V10 = UC_CPU_PPC_E500V2_V10,
+    UC_CPU_PPC_MPC8548E_V11 = UC_CPU_PPC_E500V2_V11,
+    UC_CPU_PPC_MPC8548E_V20 = UC_CPU_PPC_E500V2_V20,
+    UC_CPU_PPC_MPC8548E_V21 = UC_CPU_PPC_E500V2_V21,
+    UC_CPU_PPC_MPC8555_V10 = UC_CPU_PPC_E500V2_V10,
+    UC_CPU_PPC_MPC8555_V11 = UC_CPU_PPC_E500V2_V11,
+    UC_CPU_PPC_MPC8555E_V10 = UC_CPU_PPC_E500V2_V10,
+    UC_CPU_PPC_MPC8555E_V11 = UC_CPU_PPC_E500V2_V11,
+    UC_CPU_PPC_MPC8560_V10 = UC_CPU_PPC_E500V2_V10,
+    UC_CPU_PPC_MPC8560_V20 = UC_CPU_PPC_E500V2_V20,
+    UC_CPU_PPC_MPC8560_V21 = UC_CPU_PPC_E500V2_V21,
+    UC_CPU_PPC_MPC8567 = UC_CPU_PPC_E500V2_V22,
+    UC_CPU_PPC_MPC8567E = UC_CPU_PPC_E500V2_V22,
+    UC_CPU_PPC_MPC8568 = UC_CPU_PPC_E500V2_V22,
+    UC_CPU_PPC_MPC8568E = UC_CPU_PPC_E500V2_V22,
+    UC_CPU_PPC_MPC8572 = UC_CPU_PPC_E500V2_V30,
+    UC_CPU_PPC_MPC8572E = UC_CPU_PPC_E500V2_V30,
+    UC_CPU_PPC_MPC8610 = UC_CPU_PPC_E600,
+    UC_CPU_PPC_MPC8641 = UC_CPU_PPC_E600,
+    UC_CPU_PPC_MPC8641D = UC_CPU_PPC_E600,
+} uc_cpu_ppc;
+
+typedef enum uc_cpu_ppc64 {
+    UC_CPU_PPC64_620 = 0,
+    UC_CPU_PPC64_630,
+    UC_CPU_PPC64_631,
+    UC_CPU_PPC64_POWER4,
+    UC_CPU_PPC64_POWER4P,
+    UC_CPU_PPC64_POWER5,
+    UC_CPU_PPC64_POWER5P_V21,
+    UC_CPU_PPC64_POWER6,
+    UC_CPU_PPC64_POWER_SERVER_MASK,
+    UC_CPU_PPC64_POWER7_BASE,
+    UC_CPU_PPC64_POWER7_V23,
+    UC_CPU_PPC64_POWER7P_BASE,
+    UC_CPU_PPC64_POWER7P_V21,
+    UC_CPU_PPC64_POWER8E_BASE,
+    UC_CPU_PPC64_POWER8E_V21,
+    UC_CPU_PPC64_POWER8_BASE,
+    UC_CPU_PPC64_POWER8_V20,
+    UC_CPU_PPC64_POWER8NVL_BASE,
+    UC_CPU_PPC64_POWER8NVL_V10,
+    UC_CPU_PPC64_POWER9_BASE,
+    UC_CPU_PPC64_POWER9_DD1,
+    UC_CPU_PPC64_POWER9_DD20,
+    UC_CPU_PPC64_POWER10_BASE,
+    UC_CPU_PPC64_POWER10_DD1,
+    UC_CPU_PPC64_970_V22,
+    UC_CPU_PPC64_970FX_V10,
+    UC_CPU_PPC64_970FX_V20,
+    UC_CPU_PPC64_970FX_V21,
+    UC_CPU_PPC64_970FX_V30,
+    UC_CPU_PPC64_970FX_V31,
+    UC_CPU_PPC64_970MP_V10,
+    UC_CPU_PPC64_970MP_V11,
+    UC_CPU_PPC64_CELL_V10,
+    UC_CPU_PPC64_CELL_V20,
+    UC_CPU_PPC64_CELL_V30,
+    UC_CPU_PPC64_CELL_V31,
+    UC_CPU_PPC64_RS64,
+    UC_CPU_PPC64_RS64II,
+    UC_CPU_PPC64_RS64III,
+    UC_CPU_PPC64_RS64IV,
+    UC_CPU_PPC64_CELL_V32 = UC_CPU_PPC64_CELL_V31,
+    UC_CPU_PPC64_CELL = UC_CPU_PPC64_CELL_V32,
+} uc_cpu_ppc64;
+
 //> PPC registers
 typedef enum uc_ppc_reg {
     UC_PPC_REG_INVALID = 0,

include/unicorn/riscv.h

@@ -12,9 +12,23 @@ extern "C" {
 #endif
 
 #ifdef _MSC_VER
-#pragma warning(disable:4201)
+#pragma warning(disable : 4201)
 #endif
 
+typedef enum uc_cpu_riscv32 {
+    UC_CPU_RISCV32_ANY = 0,
+    UC_CPU_RISCV32_BASE32,
+    UC_CPU_RISCV32_SIFIVE_E31,
+    UC_CPU_RISCV32_SIFIVE_U34,
+} uc_cpu_riscv32;
+
+typedef enum uc_cpu_riscv64 {
+    UC_CPU_RISCV64_ANY = 0,
+    UC_CPU_RISCV64_BASE64,
+    UC_CPU_RISCV64_SIFIVE_E51,
+    UC_CPU_RISCV64_SIFIVE_U54,
+} uc_cpu_riscv64;
+
 //> RISCV registers
 typedef enum uc_riscv_reg {
     UC_RISCV_REG_INVALID = 0,
@@ -53,111 +67,111 @@ typedef enum uc_riscv_reg {
     UC_RISCV_REG_X31,
 
     //> Floating-point registers
-    UC_RISCV_REG_F0,    // "ft0"
-    UC_RISCV_REG_F1,    // "ft1"
-    UC_RISCV_REG_F2,    // "ft2"
-    UC_RISCV_REG_F3,    // "ft3"
-    UC_RISCV_REG_F4,    // "ft4"
-    UC_RISCV_REG_F5,    // "ft5"
-    UC_RISCV_REG_F6,    // "ft6"
-    UC_RISCV_REG_F7,    // "ft7"
-    UC_RISCV_REG_F8,    // "fs0"
-    UC_RISCV_REG_F9,    // "fs1"
-    UC_RISCV_REG_F10,   // "fa0"
-    UC_RISCV_REG_F11,   // "fa1"
-    UC_RISCV_REG_F12,   // "fa2"
-    UC_RISCV_REG_F13,   // "fa3"
-    UC_RISCV_REG_F14,   // "fa4"
-    UC_RISCV_REG_F15,   // "fa5"
-    UC_RISCV_REG_F16,   // "fa6"
-    UC_RISCV_REG_F17,   // "fa7"
-    UC_RISCV_REG_F18,   // "fs2"
-    UC_RISCV_REG_F19,   // "fs3"
-    UC_RISCV_REG_F20,   // "fs4"
-    UC_RISCV_REG_F21,   // "fs5"
-    UC_RISCV_REG_F22,   // "fs6"
-    UC_RISCV_REG_F23,   // "fs7"
-    UC_RISCV_REG_F24,   // "fs8"
-    UC_RISCV_REG_F25,   // "fs9"
-    UC_RISCV_REG_F26,   // "fs10"
-    UC_RISCV_REG_F27,   // "fs11"
-    UC_RISCV_REG_F28,   // "ft8"
-    UC_RISCV_REG_F29,   // "ft9"
-    UC_RISCV_REG_F30,   // "ft10"
-    UC_RISCV_REG_F31,   // "ft11"
+    UC_RISCV_REG_F0,  // "ft0"
+    UC_RISCV_REG_F1,  // "ft1"
+    UC_RISCV_REG_F2,  // "ft2"
+    UC_RISCV_REG_F3,  // "ft3"
+    UC_RISCV_REG_F4,  // "ft4"
+    UC_RISCV_REG_F5,  // "ft5"
+    UC_RISCV_REG_F6,  // "ft6"
+    UC_RISCV_REG_F7,  // "ft7"
+    UC_RISCV_REG_F8,  // "fs0"
+    UC_RISCV_REG_F9,  // "fs1"
+    UC_RISCV_REG_F10, // "fa0"
+    UC_RISCV_REG_F11, // "fa1"
+    UC_RISCV_REG_F12, // "fa2"
+    UC_RISCV_REG_F13, // "fa3"
+    UC_RISCV_REG_F14, // "fa4"
+    UC_RISCV_REG_F15, // "fa5"
+    UC_RISCV_REG_F16, // "fa6"
+    UC_RISCV_REG_F17, // "fa7"
+    UC_RISCV_REG_F18, // "fs2"
+    UC_RISCV_REG_F19, // "fs3"
+    UC_RISCV_REG_F20, // "fs4"
+    UC_RISCV_REG_F21, // "fs5"
+    UC_RISCV_REG_F22, // "fs6"
+    UC_RISCV_REG_F23, // "fs7"
+    UC_RISCV_REG_F24, // "fs8"
+    UC_RISCV_REG_F25, // "fs9"
+    UC_RISCV_REG_F26, // "fs10"
+    UC_RISCV_REG_F27, // "fs11"
+    UC_RISCV_REG_F28, // "ft8"
+    UC_RISCV_REG_F29, // "ft9"
+    UC_RISCV_REG_F30, // "ft10"
+    UC_RISCV_REG_F31, // "ft11"
 
-    UC_RISCV_REG_PC,    // PC register
+    UC_RISCV_REG_PC, // PC register
 
-    UC_RISCV_REG_ENDING,	// <-- mark the end of the list or registers
+    UC_RISCV_REG_ENDING, // <-- mark the end of the list or registers
 
     //> Alias registers
-    UC_RISCV_REG_ZERO = UC_RISCV_REG_X0,    // "zero"
-    UC_RISCV_REG_RA   = UC_RISCV_REG_X1,    // "ra"
-    UC_RISCV_REG_SP   = UC_RISCV_REG_X2,    // "sp"
-    UC_RISCV_REG_GP   = UC_RISCV_REG_X3,    // "gp"
-    UC_RISCV_REG_TP   = UC_RISCV_REG_X4,    // "tp"
-    UC_RISCV_REG_T0   = UC_RISCV_REG_X5,    // "t0"
-    UC_RISCV_REG_T1   = UC_RISCV_REG_X6,    // "t1"
-    UC_RISCV_REG_T2   = UC_RISCV_REG_X7,    // "t2"
-    UC_RISCV_REG_S0   = UC_RISCV_REG_X8,    // "s0"
-    UC_RISCV_REG_FP   = UC_RISCV_REG_X8,    // "fp"
-    UC_RISCV_REG_S1   = UC_RISCV_REG_X9,    // "s1"
-    UC_RISCV_REG_A0   = UC_RISCV_REG_X10,   // "a0"
-    UC_RISCV_REG_A1   = UC_RISCV_REG_X11,   // "a1"
-    UC_RISCV_REG_A2   = UC_RISCV_REG_X12,   // "a2"
-    UC_RISCV_REG_A3   = UC_RISCV_REG_X13,   // "a3"
-    UC_RISCV_REG_A4   = UC_RISCV_REG_X14,   // "a4"
-    UC_RISCV_REG_A5   = UC_RISCV_REG_X15,   // "a5"
-    UC_RISCV_REG_A6   = UC_RISCV_REG_X16,   // "a6"
-    UC_RISCV_REG_A7   = UC_RISCV_REG_X17,   // "a7"
-    UC_RISCV_REG_S2   = UC_RISCV_REG_X18,   // "s2"
-    UC_RISCV_REG_S3   = UC_RISCV_REG_X19,   // "s3"
-    UC_RISCV_REG_S4   = UC_RISCV_REG_X20,   // "s4"
-    UC_RISCV_REG_S5   = UC_RISCV_REG_X21,   // "s5"
-    UC_RISCV_REG_S6   = UC_RISCV_REG_X22,   // "s6"
-    UC_RISCV_REG_S7   = UC_RISCV_REG_X23,   // "s7"
-    UC_RISCV_REG_S8   = UC_RISCV_REG_X24,   // "s8"
-    UC_RISCV_REG_S9   = UC_RISCV_REG_X25,   // "s9"
-    UC_RISCV_REG_S10  = UC_RISCV_REG_X26,   // "s10"
-    UC_RISCV_REG_S11  = UC_RISCV_REG_X27,   // "s11"
-    UC_RISCV_REG_T3   = UC_RISCV_REG_X28,   // "t3"
-    UC_RISCV_REG_T4   = UC_RISCV_REG_X29,   // "t4"
-    UC_RISCV_REG_T5   = UC_RISCV_REG_X30,   // "t5"
-    UC_RISCV_REG_T6   = UC_RISCV_REG_X31,   // "t6"
+    UC_RISCV_REG_ZERO = UC_RISCV_REG_X0, // "zero"
+    UC_RISCV_REG_RA = UC_RISCV_REG_X1,   // "ra"
+    UC_RISCV_REG_SP = UC_RISCV_REG_X2,   // "sp"
+    UC_RISCV_REG_GP = UC_RISCV_REG_X3,   // "gp"
+    UC_RISCV_REG_TP = UC_RISCV_REG_X4,   // "tp"
+    UC_RISCV_REG_T0 = UC_RISCV_REG_X5,   // "t0"
+    UC_RISCV_REG_T1 = UC_RISCV_REG_X6,   // "t1"
+    UC_RISCV_REG_T2 = UC_RISCV_REG_X7,   // "t2"
+    UC_RISCV_REG_S0 = UC_RISCV_REG_X8,   // "s0"
+    UC_RISCV_REG_FP = UC_RISCV_REG_X8,   // "fp"
+    UC_RISCV_REG_S1 = UC_RISCV_REG_X9,   // "s1"
+    UC_RISCV_REG_A0 = UC_RISCV_REG_X10,  // "a0"
+    UC_RISCV_REG_A1 = UC_RISCV_REG_X11,  // "a1"
+    UC_RISCV_REG_A2 = UC_RISCV_REG_X12,  // "a2"
+    UC_RISCV_REG_A3 = UC_RISCV_REG_X13,  // "a3"
+    UC_RISCV_REG_A4 = UC_RISCV_REG_X14,  // "a4"
+    UC_RISCV_REG_A5 = UC_RISCV_REG_X15,  // "a5"
+    UC_RISCV_REG_A6 = UC_RISCV_REG_X16,  // "a6"
+    UC_RISCV_REG_A7 = UC_RISCV_REG_X17,  // "a7"
+    UC_RISCV_REG_S2 = UC_RISCV_REG_X18,  // "s2"
+    UC_RISCV_REG_S3 = UC_RISCV_REG_X19,  // "s3"
+    UC_RISCV_REG_S4 = UC_RISCV_REG_X20,  // "s4"
+    UC_RISCV_REG_S5 = UC_RISCV_REG_X21,  // "s5"
+    UC_RISCV_REG_S6 = UC_RISCV_REG_X22,  // "s6"
+    UC_RISCV_REG_S7 = UC_RISCV_REG_X23,  // "s7"
+    UC_RISCV_REG_S8 = UC_RISCV_REG_X24,  // "s8"
+    UC_RISCV_REG_S9 = UC_RISCV_REG_X25,  // "s9"
+    UC_RISCV_REG_S10 = UC_RISCV_REG_X26, // "s10"
+    UC_RISCV_REG_S11 = UC_RISCV_REG_X27, // "s11"
+    UC_RISCV_REG_T3 = UC_RISCV_REG_X28,  // "t3"
+    UC_RISCV_REG_T4 = UC_RISCV_REG_X29,  // "t4"
+    UC_RISCV_REG_T5 = UC_RISCV_REG_X30,  // "t5"
+    UC_RISCV_REG_T6 = UC_RISCV_REG_X31,  // "t6"
 
-    UC_RISCV_REG_FT0 = UC_RISCV_REG_F0,	    // "ft0"
-    UC_RISCV_REG_FT1 = UC_RISCV_REG_F1,	    // "ft1"
-    UC_RISCV_REG_FT2 = UC_RISCV_REG_F2,	    // "ft2"
-    UC_RISCV_REG_FT3 = UC_RISCV_REG_F3,	    // "ft3"
-    UC_RISCV_REG_FT4 = UC_RISCV_REG_F4,	    // "ft4"
-    UC_RISCV_REG_FT5 = UC_RISCV_REG_F5,	    // "ft5"
-    UC_RISCV_REG_FT6 = UC_RISCV_REG_F6,	    // "ft6"
-    UC_RISCV_REG_FT7 = UC_RISCV_REG_F7,	    // "ft7"
-    UC_RISCV_REG_FS0 = UC_RISCV_REG_F8,	    // "fs0"
-    UC_RISCV_REG_FS1 = UC_RISCV_REG_F9,	    // "fs1"
+    UC_RISCV_REG_FT0 = UC_RISCV_REG_F0, // "ft0"
+    UC_RISCV_REG_FT1 = UC_RISCV_REG_F1, // "ft1"
+    UC_RISCV_REG_FT2 = UC_RISCV_REG_F2, // "ft2"
+    UC_RISCV_REG_FT3 = UC_RISCV_REG_F3, // "ft3"
+    UC_RISCV_REG_FT4 = UC_RISCV_REG_F4, // "ft4"
+    UC_RISCV_REG_FT5 = UC_RISCV_REG_F5, // "ft5"
+    UC_RISCV_REG_FT6 = UC_RISCV_REG_F6, // "ft6"
+    UC_RISCV_REG_FT7 = UC_RISCV_REG_F7, // "ft7"
+    UC_RISCV_REG_FS0 = UC_RISCV_REG_F8, // "fs0"
+    UC_RISCV_REG_FS1 = UC_RISCV_REG_F9, // "fs1"
 
-    UC_RISCV_REG_FA0 = UC_RISCV_REG_F10,    // "fa0"
-    UC_RISCV_REG_FA1 = UC_RISCV_REG_F11,    // "fa1"
-    UC_RISCV_REG_FA2 = UC_RISCV_REG_F12,    // "fa2"
-    UC_RISCV_REG_FA3 = UC_RISCV_REG_F13,    // "fa3"
-    UC_RISCV_REG_FA4 = UC_RISCV_REG_F14,    // "fa4"
-    UC_RISCV_REG_FA5 = UC_RISCV_REG_F15,    // "fa5"
-    UC_RISCV_REG_FA6 = UC_RISCV_REG_F16,    // "fa6"
-    UC_RISCV_REG_FA7 = UC_RISCV_REG_F17,    // "fa7"
-    UC_RISCV_REG_FS2 = UC_RISCV_REG_F18,    // "fs2"
-    UC_RISCV_REG_FS3 = UC_RISCV_REG_F19,    // "fs3"
-    UC_RISCV_REG_FS4 = UC_RISCV_REG_F20,    // "fs4"
-    UC_RISCV_REG_FS5 = UC_RISCV_REG_F21,    // "fs5"
-    UC_RISCV_REG_FS6 = UC_RISCV_REG_F22,    // "fs6"
-    UC_RISCV_REG_FS7 = UC_RISCV_REG_F23,    // "fs7"
-    UC_RISCV_REG_FS8 = UC_RISCV_REG_F24,    // "fs8"
-    UC_RISCV_REG_FS9 = UC_RISCV_REG_F25,    // "fs9"
-    UC_RISCV_REG_FS10 = UC_RISCV_REG_F26,   // "fs10"
-    UC_RISCV_REG_FS11 = UC_RISCV_REG_F27,   // "fs11"
-    UC_RISCV_REG_FT8 = UC_RISCV_REG_F28,    // "ft8"
-    UC_RISCV_REG_FT9 = UC_RISCV_REG_F29,    // "ft9"
-    UC_RISCV_REG_FT10 = UC_RISCV_REG_F30,   // "ft10"
-    UC_RISCV_REG_FT11 = UC_RISCV_REG_F31,   // "ft11"
+    UC_RISCV_REG_FA0 = UC_RISCV_REG_F10,  // "fa0"
+    UC_RISCV_REG_FA1 = UC_RISCV_REG_F11,  // "fa1"
+    UC_RISCV_REG_FA2 = UC_RISCV_REG_F12,  // "fa2"
+    UC_RISCV_REG_FA3 = UC_RISCV_REG_F13,  // "fa3"
+    UC_RISCV_REG_FA4 = UC_RISCV_REG_F14,  // "fa4"
+    UC_RISCV_REG_FA5 = UC_RISCV_REG_F15,  // "fa5"
+    UC_RISCV_REG_FA6 = UC_RISCV_REG_F16,  // "fa6"
+    UC_RISCV_REG_FA7 = UC_RISCV_REG_F17,  // "fa7"
+    UC_RISCV_REG_FS2 = UC_RISCV_REG_F18,  // "fs2"
+    UC_RISCV_REG_FS3 = UC_RISCV_REG_F19,  // "fs3"
+    UC_RISCV_REG_FS4 = UC_RISCV_REG_F20,  // "fs4"
+    UC_RISCV_REG_FS5 = UC_RISCV_REG_F21,  // "fs5"
+    UC_RISCV_REG_FS6 = UC_RISCV_REG_F22,  // "fs6"
+    UC_RISCV_REG_FS7 = UC_RISCV_REG_F23,  // "fs7"
+    UC_RISCV_REG_FS8 = UC_RISCV_REG_F24,  // "fs8"
+    UC_RISCV_REG_FS9 = UC_RISCV_REG_F25,  // "fs9"
+    UC_RISCV_REG_FS10 = UC_RISCV_REG_F26, // "fs10"
+    UC_RISCV_REG_FS11 = UC_RISCV_REG_F27, // "fs11"
+    UC_RISCV_REG_FT8 = UC_RISCV_REG_F28,  // "ft8"
+    UC_RISCV_REG_FT9 = UC_RISCV_REG_F29,  // "ft9"
+    UC_RISCV_REG_FT10 = UC_RISCV_REG_F30, // "ft10"
+    UC_RISCV_REG_FT11 = UC_RISCV_REG_F31, // "ft11"
 } uc_riscv_reg;
 
 #ifdef __cplusplus

include/unicorn/sparc.h

@@ -16,9 +16,45 @@ extern "C" {
 #undef sparc
 
 #ifdef _MSC_VER
-#pragma warning(disable:4201)
+#pragma warning(disable : 4201)
 #endif
 
+typedef enum uc_cpu_sparc {
+    UC_CPU_SPARC_FUJITSU_MB86904 = 0,
+    UC_CPU_SPARC_FUJITSU_MB86907,
+    UC_CPU_SPARC_TI_MICROSPARC_I,
+    UC_CPU_SPARC_TI_MICROSPARC_II,
+    UC_CPU_SPARC_TI_MICROSPARC_IIEP,
+    UC_CPU_SPARC_TI_SUPERSPARC_40,
+    UC_CPU_SPARC_TI_SUPERSPARC_50,
+    UC_CPU_SPARC_TI_SUPERSPARC_51,
+    UC_CPU_SPARC_TI_SUPERSPARC_60,
+    UC_CPU_SPARC_TI_SUPERSPARC_61,
+    UC_CPU_SPARC_TI_SUPERSPARC_II,
+    UC_CPU_SPARC_LEON2,
+    UC_CPU_SPARC_LEON3
+} uc_cpu_sparc;
+
+typedef enum uc_cpu_sparc64 {
+    UC_CPU_SPARC64_FUJITSU = 0,
+    UC_CPU_SPARC64_FUJITSU_III,
+    UC_CPU_SPARC64_FUJITSU_IV,
+    UC_CPU_SPARC64_FUJITSU_V,
+    UC_CPU_SPARC64_TI_ULTRASPARC_I,
+    UC_CPU_SPARC64_TI_ULTRASPARC_II,
+    UC_CPU_SPARC64_TI_ULTRASPARC_III,
+    UC_CPU_SPARC64_TI_ULTRASPARC_IIE,
+    UC_CPU_SPARC64_SUN_ULTRASPARC_III,
+    UC_CPU_SPARC64_SUN_ULTRASPARC_III_CU,
+    UC_CPU_SPARC64_SUN_ULTRASPARC_IIII,
+    UC_CPU_SPARC64_SUN_ULTRASPARC_IV,
+    UC_CPU_SPARC64_SUN_ULTRASPARC_IV_PLUS,
+    UC_CPU_SPARC64_SUN_ULTRASPARC_IIII_PLUS,
+    UC_CPU_SPARC64_SUN_ULTRASPARC_T1,
+    UC_CPU_SPARC64_SUN_ULTRASPARC_T2,
+    UC_CPU_SPARC64_NEC_ULTRASPARC_I,
+} uc_cpu_sparc64;
+
 //> SPARC registers
 typedef enum uc_sparc_reg {
     UC_SPARC_REG_INVALID = 0,
@@ -71,7 +107,7 @@ typedef enum uc_sparc_reg {
     UC_SPARC_REG_F58,
     UC_SPARC_REG_F60,
     UC_SPARC_REG_F62,
-    UC_SPARC_REG_FCC0,	// Floating condition codes
+    UC_SPARC_REG_FCC0, // Floating condition codes
     UC_SPARC_REG_FCC1,
     UC_SPARC_REG_FCC2,
     UC_SPARC_REG_FCC3,
@@ -91,7 +127,7 @@ typedef enum uc_sparc_reg {
     UC_SPARC_REG_I5,
     UC_SPARC_REG_FP,
     UC_SPARC_REG_I7,
-    UC_SPARC_REG_ICC,	// Integer condition codes
+    UC_SPARC_REG_ICC, // Integer condition codes
     UC_SPARC_REG_L0,
     UC_SPARC_REG_L1,
     UC_SPARC_REG_L2,
@@ -114,9 +150,9 @@ typedef enum uc_sparc_reg {
     UC_SPARC_REG_XCC,
 
     // pseudo register
-    UC_SPARC_REG_PC,   // program counter register
+    UC_SPARC_REG_PC, // program counter register
 
-    UC_SPARC_REG_ENDING,   // <-- mark the end of the list of registers
+    UC_SPARC_REG_ENDING, // <-- mark the end of the list of registers
 
     // extras
     UC_SPARC_REG_O6 = UC_SPARC_REG_SP,

include/unicorn/unicorn.h

@@ -42,11 +42,11 @@ typedef size_t uc_hook;
 #endif
 
 #ifdef _MSC_VER
-#pragma warning(disable:4201)
-#pragma warning(disable:4100)
+#pragma warning(disable : 4201)
+#pragma warning(disable : 4100)
 #ifdef UNICORN_SHARED
 #define UNICORN_EXPORT __declspec(dllexport)
-#else    // defined(UNICORN_STATIC)
+#else // defined(UNICORN_STATIC)
 #define UNICORN_EXPORT
 #endif
 #else
@@ -62,7 +62,8 @@ typedef size_t uc_hook;
 #elif defined(_MSC_VER)
 #define UNICORN_DEPRECATED __declspec(deprecated)
 #else
-#pragma message("WARNING: You need to implement UNICORN_DEPRECATED for this compiler")
+#pragma message(                                                               \
+    "WARNING: You need to implement UNICORN_DEPRECATED for this compiler")
 #define UNICORN_DEPRECATED
 #endif
 
@@ -75,7 +76,6 @@ typedef size_t uc_hook;
 #define UC_VERSION_MINOR UC_API_MINOR
 #define UC_VERSION_EXTRA 0
 
-
 /*
   Macro to create combined version which can be compared to
   result of uc_version() API.
@@ -90,14 +90,14 @@ typedef size_t uc_hook;
 
 // Architecture type
 typedef enum uc_arch {
-    UC_ARCH_ARM = 1,    // ARM architecture (including Thumb, Thumb-2)
-    UC_ARCH_ARM64,      // ARM-64, also called AArch64
-    UC_ARCH_MIPS,       // Mips architecture
-    UC_ARCH_X86,        // X86 architecture (including x86 & x86-64)
-    UC_ARCH_PPC,        // PowerPC architecture
-    UC_ARCH_SPARC,      // Sparc architecture
-    UC_ARCH_M68K,       // M68K architecture
-    UC_ARCH_RISCV,      // RISCV architecture
+    UC_ARCH_ARM = 1, // ARM architecture (including Thumb, Thumb-2)
+    UC_ARCH_ARM64,   // ARM-64, also called AArch64
+    UC_ARCH_MIPS,    // Mips architecture
+    UC_ARCH_X86,     // X86 architecture (including x86 & x86-64)
+    UC_ARCH_PPC,     // PowerPC architecture
+    UC_ARCH_SPARC,   // Sparc architecture
+    UC_ARCH_M68K,    // M68K architecture
+    UC_ARCH_RISCV,   // RISCV architecture
     UC_ARCH_MAX,
 } uc_arch;
 
@@ -107,41 +107,42 @@ typedef enum uc_mode {
     UC_MODE_BIG_ENDIAN = 1 << 30, // big-endian mode
 
     // arm / arm64
-    UC_MODE_ARM = 0,              // ARM mode
-    UC_MODE_THUMB = 1 << 4,       // THUMB mode (including Thumb-2)
-    UC_MODE_MCLASS = 1 << 5,      // ARM's Cortex-M series
-    UC_MODE_V8 = 1 << 6,          // ARMv8 A32 encodings for ARM (currently unsupported)
+    UC_MODE_ARM = 0,         // ARM mode
+    UC_MODE_THUMB = 1 << 4,  // THUMB mode (including Thumb-2)
+    UC_MODE_MCLASS = 1 << 5, // ARM's Cortex-M series
+    UC_MODE_V8 = 1 << 6, // ARMv8 A32 encodings for ARM (currently unsupported)
 
     // arm (32bit) cpu types
-    UC_MODE_ARM926 = 1 << 7,	  // ARM926 CPU type
-    UC_MODE_ARM946 = 1 << 8,	  // ARM946 CPU type
-    UC_MODE_ARM1176 = 1 << 9,	  // ARM1176 CPU type
+    UC_MODE_ARM926 = 1 << 7,  // ARM926 CPU type
+    UC_MODE_ARM946 = 1 << 8,  // ARM946 CPU type
+    UC_MODE_ARM1176 = 1 << 9, // ARM1176 CPU type
 
     // mips
-    UC_MODE_MICRO = 1 << 4,       // MicroMips mode (currently unsupported)
-    UC_MODE_MIPS3 = 1 << 5,       // Mips III ISA (currently unsupported)
-    UC_MODE_MIPS32R6 = 1 << 6,    // Mips32r6 ISA (currently unsupported)
-    UC_MODE_MIPS32 = 1 << 2,      // Mips32 ISA
-    UC_MODE_MIPS64 = 1 << 3,      // Mips64 ISA
+    UC_MODE_MICRO = 1 << 4,    // MicroMips mode (currently unsupported)
+    UC_MODE_MIPS3 = 1 << 5,    // Mips III ISA (currently unsupported)
+    UC_MODE_MIPS32R6 = 1 << 6, // Mips32r6 ISA (currently unsupported)
+    UC_MODE_MIPS32 = 1 << 2,   // Mips32 ISA
+    UC_MODE_MIPS64 = 1 << 3,   // Mips64 ISA
 
     // x86 / x64
-    UC_MODE_16 = 1 << 1,          // 16-bit mode
-    UC_MODE_32 = 1 << 2,          // 32-bit mode
-    UC_MODE_64 = 1 << 3,          // 64-bit mode
+    UC_MODE_16 = 1 << 1, // 16-bit mode
+    UC_MODE_32 = 1 << 2, // 32-bit mode
+    UC_MODE_64 = 1 << 3, // 64-bit mode
 
-    // ppc 
-    UC_MODE_PPC32 = 1 << 2,       // 32-bit mode
-    UC_MODE_PPC64 = 1 << 3,       // 64-bit mode (currently unsupported)
-    UC_MODE_QPX = 1 << 4,         // Quad Processing eXtensions mode (currently unsupported)
+    // ppc
+    UC_MODE_PPC32 = 1 << 2, // 32-bit mode
+    UC_MODE_PPC64 = 1 << 3, // 64-bit mode (currently unsupported)
+    UC_MODE_QPX =
+        1 << 4, // Quad Processing eXtensions mode (currently unsupported)
 
     // sparc
-    UC_MODE_SPARC32 = 1 << 2,     // 32-bit mode
-    UC_MODE_SPARC64 = 1 << 3,     // 64-bit mode
-    UC_MODE_V9 = 1 << 4,          // SparcV9 mode (currently unsupported)
+    UC_MODE_SPARC32 = 1 << 2, // 32-bit mode
+    UC_MODE_SPARC64 = 1 << 3, // 64-bit mode
+    UC_MODE_V9 = 1 << 4,      // SparcV9 mode (currently unsupported)
 
     // riscv
-    UC_MODE_RISCV32 = 1 << 2,     // 32-bit mode
-    UC_MODE_RISCV64 = 1 << 3,     // 64-bit mode
+    UC_MODE_RISCV32 = 1 << 2, // 32-bit mode
+    UC_MODE_RISCV64 = 1 << 3, // 64-bit mode
 
     // m68k
 } uc_mode;
@@ -149,39 +150,48 @@ typedef enum uc_mode {
 // All type of errors encountered by Unicorn API.
 // These are values returned by uc_errno()
 typedef enum uc_err {
-    UC_ERR_OK = 0,   // No error: everything was fine
-    UC_ERR_NOMEM,      // Out-Of-Memory error: uc_open(), uc_emulate()
-    UC_ERR_ARCH,     // Unsupported architecture: uc_open()
-    UC_ERR_HANDLE,   // Invalid handle
-    UC_ERR_MODE,     // Invalid/unsupported mode: uc_open()
-    UC_ERR_VERSION,  // Unsupported version (bindings)
-    UC_ERR_READ_UNMAPPED, // Quit emulation due to READ on unmapped memory: uc_emu_start()
-    UC_ERR_WRITE_UNMAPPED, // Quit emulation due to WRITE on unmapped memory: uc_emu_start()
-    UC_ERR_FETCH_UNMAPPED, // Quit emulation due to FETCH on unmapped memory: uc_emu_start()
-    UC_ERR_HOOK,    // Invalid hook type: uc_hook_add()
-    UC_ERR_INSN_INVALID, // Quit emulation due to invalid instruction: uc_emu_start()
-    UC_ERR_MAP, // Invalid memory mapping: uc_mem_map()
-    UC_ERR_WRITE_PROT, // Quit emulation due to UC_MEM_WRITE_PROT violation: uc_emu_start()
-    UC_ERR_READ_PROT, // Quit emulation due to UC_MEM_READ_PROT violation: uc_emu_start()
-    UC_ERR_FETCH_PROT, // Quit emulation due to UC_MEM_FETCH_PROT violation: uc_emu_start()
-    UC_ERR_ARG,     // Inavalid argument provided to uc_xxx function (See specific function API)
+    UC_ERR_OK = 0,         // No error: everything was fine
+    UC_ERR_NOMEM,          // Out-Of-Memory error: uc_open(), uc_emulate()
+    UC_ERR_ARCH,           // Unsupported architecture: uc_open()
+    UC_ERR_HANDLE,         // Invalid handle
+    UC_ERR_MODE,           // Invalid/unsupported mode: uc_open()
+    UC_ERR_VERSION,        // Unsupported version (bindings)
+    UC_ERR_READ_UNMAPPED,  // Quit emulation due to READ on unmapped memory:
+                           // uc_emu_start()
+    UC_ERR_WRITE_UNMAPPED, // Quit emulation due to WRITE on unmapped memory:
+                           // uc_emu_start()
+    UC_ERR_FETCH_UNMAPPED, // Quit emulation due to FETCH on unmapped memory:
+                           // uc_emu_start()
+    UC_ERR_HOOK,           // Invalid hook type: uc_hook_add()
+    UC_ERR_INSN_INVALID,   // Quit emulation due to invalid instruction:
+                           // uc_emu_start()
+    UC_ERR_MAP,            // Invalid memory mapping: uc_mem_map()
+    UC_ERR_WRITE_PROT,     // Quit emulation due to UC_MEM_WRITE_PROT violation:
+                           // uc_emu_start()
+    UC_ERR_READ_PROT,      // Quit emulation due to UC_MEM_READ_PROT violation:
+                           // uc_emu_start()
+    UC_ERR_FETCH_PROT,     // Quit emulation due to UC_MEM_FETCH_PROT violation:
+                           // uc_emu_start()
+    UC_ERR_ARG, // Inavalid argument provided to uc_xxx function (See specific
+                // function API)
     UC_ERR_READ_UNALIGNED,  // Unaligned read
-    UC_ERR_WRITE_UNALIGNED,  // Unaligned write
-    UC_ERR_FETCH_UNALIGNED,  // Unaligned fetch
-    UC_ERR_HOOK_EXIST,  // hook for this event already existed
-    UC_ERR_RESOURCE,    // Insufficient resource: uc_emu_start()
-    UC_ERR_EXCEPTION, // Unhandled CPU exception
+    UC_ERR_WRITE_UNALIGNED, // Unaligned write
+    UC_ERR_FETCH_UNALIGNED, // Unaligned fetch
+    UC_ERR_HOOK_EXIST,      // hook for this event already existed
+    UC_ERR_RESOURCE,        // Insufficient resource: uc_emu_start()
+    UC_ERR_EXCEPTION,       // Unhandled CPU exception
 } uc_err;
 
-
 /*
   Callback function for tracing code (UC_HOOK_CODE & UC_HOOK_BLOCK)
 
   @address: address where the code is being executed
-  @size: size of machine instruction(s) being executed, or 0 when size is unknown
+  @size: size of machine instruction(s) being executed, or 0 when size is
+  unknown
   @user_data: user data passed to tracing APIs.
 */
-typedef void (*uc_cb_hookcode_t)(uc_engine *uc, uint64_t address, uint32_t size, void *user_data);
+typedef void (*uc_cb_hookcode_t)(uc_engine *uc, uint64_t address, uint32_t size,
+                                 void *user_data);
 
 /*
   Callback function for tracing interrupts (for uc_hook_intr())
@@ -189,14 +199,16 @@ typedef void (*uc_cb_hookcode_t)(uc_engine *uc, uint64_t address, uint32_t size,
   @intno: interrupt number
   @user_data: user data passed to tracing APIs.
 */
-typedef void (*uc_cb_hookintr_t)(uc_engine *uc, uint32_t intno, void *user_data);
+typedef void (*uc_cb_hookintr_t)(uc_engine *uc, uint32_t intno,
+                                 void *user_data);
 
 /*
   Callback function for tracing invalid instructions
 
   @user_data: user data passed to tracing APIs.
 
-  @return: return true to continue, or false to stop program (due to invalid instruction).
+  @return: return true to continue, or false to stop program (due to invalid
+  instruction).
 */
 typedef bool (*uc_cb_hookinsn_invalid_t)(uc_engine *uc, void *user_data);
 
@@ -207,7 +219,8 @@ typedef bool (*uc_cb_hookinsn_invalid_t)(uc_engine *uc, void *user_data);
   @size: data size (1/2/4) to be read from this port
   @user_data: user data passed to tracing APIs.
 */
-typedef uint32_t (*uc_cb_insn_in_t)(uc_engine *uc, uint32_t port, int size, void *user_data);
+typedef uint32_t (*uc_cb_insn_in_t)(uc_engine *uc, uint32_t port, int size,
+                                    void *user_data);
 
 /*
   Callback function for OUT instruction of X86
@@ -216,7 +229,24 @@ typedef uint32_t (*uc_cb_insn_in_t)(uc_engine *uc, uint32_t port, int size, void
   @size: data size (1/2/4) to be written to this port
   @value: data value to be written to this port
 */
-typedef void (*uc_cb_insn_out_t)(uc_engine *uc, uint32_t port, int size, uint32_t value, void *user_data);
+typedef void (*uc_cb_insn_out_t)(uc_engine *uc, uint32_t port, int size,
+                                 uint32_t value, void *user_data);
+
+// Represent a TranslationBlock.
+typedef struct uc_tb {
+    uint64_t pc;
+    uint16_t icount;
+    uint16_t size;
+} uc_tb;
+
+/*
+  Callback function for new edges between translation blocks.
+
+  @cur_tb: Current TB which is to be generated.
+  @prev_tb: The previous TB.
+*/
+typedef void (*uc_hook_edge_gen_t)(uc_engine *uc, uc_tb *cur_tb, uc_tb *prev_tb,
+                                   void *user_data);
 
 /*
   Callback function for MMIO read
@@ -225,7 +255,8 @@ typedef void (*uc_cb_insn_out_t)(uc_engine *uc, uint32_t port, int size, uint32_
   @size: data size to read
   @user_data: user data passed to uc_mmio_map()
 */
-typedef uint64_t (*uc_cb_mmio_read_t)(uc_engine *uc, uint64_t offset, unsigned size, void *user_data);
+typedef uint64_t (*uc_cb_mmio_read_t)(uc_engine *uc, uint64_t offset,
+                                      unsigned size, void *user_data);
 
 /*
   Callback function for MMIO write
@@ -235,28 +266,30 @@ typedef uint64_t (*uc_cb_mmio_read_t)(uc_engine *uc, uint64_t offset, unsigned s
   @value: data value to be written
   @user_data: user data passed to uc_mmio_map()
 */
-typedef void (*uc_cb_mmio_write_t)(uc_engine *uc, uint64_t offset, unsigned size, uint64_t value, void *user_data);
-
+typedef void (*uc_cb_mmio_write_t)(uc_engine *uc, uint64_t offset,
+                                   unsigned size, uint64_t value,
+                                   void *user_data);
 
 // All type of memory accesses for UC_HOOK_MEM_*
 typedef enum uc_mem_type {
-    UC_MEM_READ = 16,   // Memory is read from
-    UC_MEM_WRITE,       // Memory is written to
-    UC_MEM_FETCH,       // Memory is fetched
-    UC_MEM_READ_UNMAPPED,    // Unmapped memory is read from
-    UC_MEM_WRITE_UNMAPPED,   // Unmapped memory is written to
-    UC_MEM_FETCH_UNMAPPED,   // Unmapped memory is fetched
-    UC_MEM_WRITE_PROT,  // Write to write protected, but mapped, memory
-    UC_MEM_READ_PROT,   // Read from read protected, but mapped, memory
-    UC_MEM_FETCH_PROT,  // Fetch from non-executable, but mapped, memory
-    UC_MEM_READ_AFTER,   // Memory is read from (successful access)
+    UC_MEM_READ = 16,      // Memory is read from
+    UC_MEM_WRITE,          // Memory is written to
+    UC_MEM_FETCH,          // Memory is fetched
+    UC_MEM_READ_UNMAPPED,  // Unmapped memory is read from
+    UC_MEM_WRITE_UNMAPPED, // Unmapped memory is written to
+    UC_MEM_FETCH_UNMAPPED, // Unmapped memory is fetched
+    UC_MEM_WRITE_PROT,     // Write to write protected, but mapped, memory
+    UC_MEM_READ_PROT,      // Read from read protected, but mapped, memory
+    UC_MEM_FETCH_PROT,     // Fetch from non-executable, but mapped, memory
+    UC_MEM_READ_AFTER,     // Memory is read from (successful access)
 } uc_mem_type;
 
 // All type of hooks for uc_hook_add() API.
 typedef enum uc_hook_type {
     // Hook all interrupt/syscall events
     UC_HOOK_INTR = 1 << 0,
-    // Hook a particular instruction - only a very small subset of instructions supported here
+    // Hook a particular instruction - only a very small subset of instructions
+    // supported here
     UC_HOOK_INSN = 1 << 1,
     // Hook a range of code
     UC_HOOK_CODE = 1 << 2,
@@ -285,24 +318,38 @@ typedef enum uc_hook_type {
     UC_HOOK_MEM_READ_AFTER = 1 << 13,
     // Hook invalid instructions exceptions.
     UC_HOOK_INSN_INVALID = 1 << 14,
+    // Hook on new edge generation. Could be useful in program analysis.
+    //
+    // NOTE: This is different from UC_HOOK_BLOCK in 2 ways:
+    //       1. The hook is called before executing code.
+    //       2. The hook is only called when generation is triggered.
+    UC_HOOK_EDGE_GENERATED = 1 << 15
 } uc_hook_type;
 
 // Hook type for all events of unmapped memory access
-#define UC_HOOK_MEM_UNMAPPED (UC_HOOK_MEM_READ_UNMAPPED + UC_HOOK_MEM_WRITE_UNMAPPED + UC_HOOK_MEM_FETCH_UNMAPPED)
+#define UC_HOOK_MEM_UNMAPPED                                                   \
+    (UC_HOOK_MEM_READ_UNMAPPED + UC_HOOK_MEM_WRITE_UNMAPPED +                  \
+     UC_HOOK_MEM_FETCH_UNMAPPED)
 // Hook type for all events of illegal protected memory access
-#define UC_HOOK_MEM_PROT (UC_HOOK_MEM_READ_PROT + UC_HOOK_MEM_WRITE_PROT + UC_HOOK_MEM_FETCH_PROT)
+#define UC_HOOK_MEM_PROT                                                       \
+    (UC_HOOK_MEM_READ_PROT + UC_HOOK_MEM_WRITE_PROT + UC_HOOK_MEM_FETCH_PROT)
 // Hook type for all events of illegal read memory access
-#define UC_HOOK_MEM_READ_INVALID (UC_HOOK_MEM_READ_PROT + UC_HOOK_MEM_READ_UNMAPPED)
+#define UC_HOOK_MEM_READ_INVALID                                               \
+    (UC_HOOK_MEM_READ_PROT + UC_HOOK_MEM_READ_UNMAPPED)
 // Hook type for all events of illegal write memory access
-#define UC_HOOK_MEM_WRITE_INVALID (UC_HOOK_MEM_WRITE_PROT + UC_HOOK_MEM_WRITE_UNMAPPED)
+#define UC_HOOK_MEM_WRITE_INVALID                                              \
+    (UC_HOOK_MEM_WRITE_PROT + UC_HOOK_MEM_WRITE_UNMAPPED)
 // Hook type for all events of illegal fetch memory access
-#define UC_HOOK_MEM_FETCH_INVALID (UC_HOOK_MEM_FETCH_PROT + UC_HOOK_MEM_FETCH_UNMAPPED)
+#define UC_HOOK_MEM_FETCH_INVALID                                              \
+    (UC_HOOK_MEM_FETCH_PROT + UC_HOOK_MEM_FETCH_UNMAPPED)
 // Hook type for all events of illegal memory access
 #define UC_HOOK_MEM_INVALID (UC_HOOK_MEM_UNMAPPED + UC_HOOK_MEM_PROT)
 // Hook type for all events of valid memory access
-// NOTE: UC_HOOK_MEM_READ is triggered before UC_HOOK_MEM_READ_PROT and UC_HOOK_MEM_READ_UNMAPPED, so
-//       this hook may technically trigger on some invalid reads. 
-#define UC_HOOK_MEM_VALID (UC_HOOK_MEM_READ + UC_HOOK_MEM_WRITE + UC_HOOK_MEM_FETCH)
+// NOTE: UC_HOOK_MEM_READ is triggered before UC_HOOK_MEM_READ_PROT and
+// UC_HOOK_MEM_READ_UNMAPPED, so
+//       this hook may technically trigger on some invalid reads.
+#define UC_HOOK_MEM_VALID                                                      \
+    (UC_HOOK_MEM_READ + UC_HOOK_MEM_WRITE + UC_HOOK_MEM_FETCH)
 
 /*
   Callback function for hooking memory (READ, WRITE & FETCH)
@@ -314,7 +361,8 @@ typedef enum uc_hook_type {
   @user_data: user data passed to tracing APIs
 */
 typedef void (*uc_cb_hookmem_t)(uc_engine *uc, uc_mem_type type,
-        uint64_t address, int size, int64_t value, void *user_data);
+                                uint64_t address, int size, int64_t value,
+                                void *user_data);
 
 /*
   Callback function for handling invalid memory access events (UNMAPPED and
@@ -326,21 +374,24 @@ typedef void (*uc_cb_hookmem_t)(uc_engine *uc, uc_mem_type type,
   @value: value of data being written to memory, or irrelevant if type = READ.
   @user_data: user data passed to tracing APIs
 
-  @return: return true to continue, or false to stop program (due to invalid memory).
-           NOTE: returning true to continue execution will only work if the accessed
-           memory is made accessible with the correct permissions during the hook.
+  @return: return true to continue, or false to stop program (due to invalid
+  memory). NOTE: returning true to continue execution will only work if the
+  accessed memory is made accessible with the correct permissions during the
+  hook.
 
-           In the event of a UC_MEM_READ_UNMAPPED or UC_MEM_WRITE_UNMAPPED callback,
-           the memory should be uc_mem_map()-ed with the correct permissions, and the
-           instruction will then read or write to the address as it was supposed to.
+           In the event of a UC_MEM_READ_UNMAPPED or UC_MEM_WRITE_UNMAPPED
+  callback, the memory should be uc_mem_map()-ed with the correct permissions,
+  and the instruction will then read or write to the address as it was supposed
+  to.
 
-           In the event of a UC_MEM_FETCH_UNMAPPED callback, the memory can be mapped
-           in as executable, in which case execution will resume from the fetched address.
-           The instruction pointer may be written to in order to change where execution resumes,
-           but the fetch must succeed if execution is to resume.
+           In the event of a UC_MEM_FETCH_UNMAPPED callback, the memory can be
+  mapped in as executable, in which case execution will resume from the fetched
+  address. The instruction pointer may be written to in order to change where
+  execution resumes, but the fetch must succeed if execution is to resume.
 */
 typedef bool (*uc_cb_eventmem_t)(uc_engine *uc, uc_mem_type type,
-        uint64_t address, int size, int64_t value, void *user_data);
+                                 uint64_t address, int size, int64_t value,
+                                 void *user_data);
 
 /*
   Memory region mapped by uc_mem_map() and uc_mem_map_ptr()
@@ -357,10 +408,116 @@ typedef enum uc_query_type {
     // Dynamically query current hardware mode.
     UC_QUERY_MODE = 1,
     UC_QUERY_PAGE_SIZE, // query pagesize of engine
-    UC_QUERY_ARCH,  // query architecture of engine (for ARM to query Thumb mode)
-    UC_QUERY_TIMEOUT,  // query if emulation stops due to timeout (indicated if result = True)
+    UC_QUERY_ARCH, // query architecture of engine (for ARM to query Thumb mode)
+    UC_QUERY_TIMEOUT, // query if emulation stops due to timeout (indicated if
+                      // result = True)
 } uc_query_type;
 
+// The implementation of uc_ctl is like what Linux ioctl does but slightly
+// different.
+//
+// A uc_control_type passed to uc_ctl is constructed as:
+//
+//    R/W       NR       Reserved     Type
+//  [      ] [      ]  [         ] [       ]
+//  31    30 29     26 25       16 15      0
+//
+//  @R/W: Whether the operation is a read or write access.
+//  @NR: Number of arguments.
+//  @Reserved: Should be zero, reserved for future extension.
+//  @Type: Taken from uc_control_type enum.
+//
+// See the helper macros below.
+
+// No input and output arguments.
+#define UC_CTL_IO_NONE (0)
+// The arguments are used for input.
+#define UC_CTL_IO_WRITE (1)
+// The arguments are used for ouput.
+#define UC_CTL_IO_READ (2)
+// The arguments include both input and output arugments.
+#define UC_CTL_IO_READ_WRITE (UC_CTL_IO_WRITE | UC_CTL_IO_READ)
+
+#define UC_CTL(type, nr, rw) ((type) | ((nr) << 26) | ((rw) << 30))
+#define UC_CTL_NONE(type, nr) UC_CTL(type, nr, UC_CTL_IO_NONE)
+#define UC_CTL_READ(type, nr) UC_CTL(type, nr, UC_CTL_IO_READ)
+#define UC_CTL_WRITE(type, nr) UC_CTL(type, nr, UC_CTL_IO_WRITE)
+#define UC_CTL_READ_WRITE(type, nr) UC_CTL(type, nr, UC_CTL_IO_READ_WRITE)
+
+// All type of controls for uc_ctl API.
+// The controls are organized in a tree level.
+// If a control don't have `Set` or `Get` for @args, it means it's r/o or w/o.
+typedef enum uc_control_type {
+    // Current mode.
+    // Read: @args = (int*)
+    UC_CTL_UC_MODE = 0,
+    // Curent page size.
+    // Write: @args = (uint32_t)
+    // Read: @args = (uint32_t*)
+    UC_CTL_UC_PAGE_SIZE,
+    // Current arch.
+    // Read: @args = (int*)
+    UC_CTL_UC_ARCH,
+    // Current timeout.
+    // Read: @args = (uint64_t*)
+    UC_CTL_UC_TIMEOUT,
+    // Enable multiple exists.
+    // Without this control, reading/setting exists won't work.
+    // This is for API backward compatibility.
+    // Write: @args = (int)
+    UC_CTL_UC_USE_EXITS,
+    // The number of current exists.
+    // Read: @args = (size_t*)
+    UC_CTL_UC_EXITS_CNT,
+    // Current exists.
+    // Write: @args = (uint64_t* exists, size_t len)
+    //        @len = UC_CTL_UC_EXITS_CNT
+    // Read: @args = (uint64_t* exists, size_t len)
+    //       @len = UC_CTL_UC_EXITS_CNT
+    UC_CTL_UC_EXITS,
+
+    // Set the cpu model of uc.
+    // Note this option can only be set before any Unicorn
+    // API is called except for uc_open.
+    // Write: @args = (int)
+    // Read:  @args = (int)
+    UC_CTL_CPU_MODEL,
+    // Request a tb cache at a specific address
+    // Read: @args = (uint64_t, uc_tb*)
+    UC_CTL_TB_REQUEST_CACHE,
+    // Invalidate a tb cache at a specific address
+    // Read: @args = (uint64_t)
+    UC_CTL_TB_REMOVE_CACHE
+
+} uc_control_type;
+
+#define uc_ctl_get_mode(uc, mode)                                              \
+    uc_ctl(uc, UC_CTL_READ(UC_CTL_UC_MODE, 1), (mode))
+#define uc_ctl_get_page_size(uc, ptr)                                          \
+    uc_ctl(uc, UC_CTL_READ(UC_CTL_UC_PAGE_SIZE, 1), (ptr))
+#define uc_ctl_set_page_size(uc, page_size)                                    \
+    uc_ctl(uc, UC_CTL_WRITE(UC_CTL_UC_PAGE_SIZE, 1), (page_size))
+#define uc_ctl_get_arch(uc, arch)                                              \
+    uc_ctl(uc, UC_CTL_READ(UC_CTL_UC_ARCH, 1), (arch))
+#define uc_ctl_get_timeout(uc, ptr)                                            \
+    uc_ctl(uc, UC_CTL_READ(UC_CTL_UC_TIMEOUT, 1), (ptr))
+#define uc_ctl_exits_enabled(uc, enabled)                                      \
+    uc_ctl(uc, UC_CTL_WRITE(UC_CTL_UC_USE_EXITS, 1), (enabled))
+#define uc_ctl_get_exists_cnt(uc, ptr)                                         \
+    uc_ctl(uc, UC_CTL_READ(UC_CTL_UC_EXITS_CNT, 1), (ptr))
+#define uc_ctl_get_exists(uc, buffer, len)                                     \
+    uc_ctl(uc, UC_CTL_READ(UC_CTL_UC_EXITS, 2), (buffer), (len))
+#define uc_ctl_set_exists(uc, buffer, len)                                     \
+    uc_ctl(uc, UC_CTL_WRITE(UC_CTL_UC_EXITS, 2), (buffer), (len))
+#define uc_ctl_get_cpu_model(uc, model)                                        \
+    uc_ctl(uc, UC_CTL_READ(UC_CTL_CPU_MODEL, 1), (model))
+#define uc_ctl_set_cpu_model(uc, model)                                        \
+    uc_ctl(uc, UC_CTL_WRITE(UC_CTL_CPU_MODEL, 1), (model))
+#define uc_ctl_remove_cache(uc, address)                                       \
+    uc_ctl(uc, UC_CTL_READ(UC_CTL_TB_REMOVE_CACHE, 1), (address))
+#define uc_ctl_request_cache(uc, address, tb)                                  \
+    uc_ctl(uc, UC_CTL_READ_WRITE(UC_CTL_TB_REQUEST_CACHE, 2), (address), (tb))
+
 // Opaque storage for CPU context, used with uc_context_*()
 struct uc_context;
 typedef struct uc_context uc_context;
@@ -385,7 +542,6 @@ typedef struct uc_context uc_context;
 UNICORN_EXPORT
 unsigned int uc_version(unsigned int *major, unsigned int *minor);
 
-
 /*
  Determine if the given architecture is supported by this library.
 
@@ -396,7 +552,6 @@ unsigned int uc_version(unsigned int *major, unsigned int *minor);
 UNICORN_EXPORT
 bool uc_arch_supported(uc_arch arch);
 
-
 /*
  Create new instance of unicorn engine.
 
@@ -439,6 +594,20 @@ uc_err uc_close(uc_engine *uc);
 UNICORN_EXPORT
 uc_err uc_query(uc_engine *uc, uc_query_type type, size_t *result);
 
+/*
+ Control internal states of engine.
+
+ Also see uc_ctl_* macro helpers for easy use.
+
+ @uc: handle returned by uc_open()
+ @option: control type.
+ @args: See uc_control_type for details about variadic arguments.
+
+ @return: error code of uc_err enum type (UC_ERR_*, see above)
+*/
+UNICORN_EXPORT
+uc_err uc_ctl(uc_engine *uc, uc_control_type option, ...);
+
 /*
  Report the last error number when some API function fails.
  Like glibc's errno, uc_errno might not retain its old value once accessed.
@@ -499,7 +668,8 @@ uc_err uc_reg_read(uc_engine *uc, int regid, void *value);
    for detailed error).
 */
 UNICORN_EXPORT
-uc_err uc_reg_write_batch(uc_engine *uc, int *regs, void *const *vals, int count);
+uc_err uc_reg_write_batch(uc_engine *uc, int *regs, void *const *vals,
+                          int count);
 
 /*
  Read multiple register values.
@@ -529,7 +699,8 @@ uc_err uc_reg_read_batch(uc_engine *uc, int *regs, void **vals, int count);
    for detailed error).
 */
 UNICORN_EXPORT
-uc_err uc_mem_write(uc_engine *uc, uint64_t address, const void *bytes, size_t size);
+uc_err uc_mem_write(uc_engine *uc, uint64_t address, const void *bytes,
+                    size_t size);
 
 /*
  Read a range of bytes in memory.
@@ -566,7 +737,8 @@ uc_err uc_mem_read(uc_engine *uc, uint64_t address, void *bytes, size_t size);
    for detailed error).
 */
 UNICORN_EXPORT
-uc_err uc_emu_start(uc_engine *uc, uint64_t begin, uint64_t until, uint64_t timeout, size_t count);
+uc_err uc_emu_start(uc_engine *uc, uint64_t begin, uint64_t until,
+                    uint64_t timeout, size_t count);
 
 /*
  Stop emulation (which was started by uc_emu_start() API.
@@ -585,15 +757,17 @@ uc_err uc_emu_stop(uc_engine *uc);
  The callback will be run when the hook event is hit.
 
  @uc: handle returned by uc_open()
- @hh: hook handle returned from this registration. To be used in uc_hook_del() API
+ @hh: hook handle returned from this registration. To be used in uc_hook_del()
+ API
  @type: hook type, refer to uc_hook_type enum
  @callback: callback to be run when instruction is hit
  @user_data: user-defined data. This will be passed to callback function in its
       last argument @user_data
  @begin: start address of the area where the callback is in effect (inclusive)
  @end: end address of the area where the callback is in effect (inclusive)
-   NOTE 1: the callback is called only if related address is in range [@begin, @end]
-   NOTE 2: if @begin > @end, callback is called whenever this hook type is triggered
+   NOTE 1: the callback is called only if related address is in range [@begin,
+ @end] NOTE 2: if @begin > @end, callback is called whenever this hook type is
+ triggered
  @...: variable arguments (depending on @type)
    NOTE: if @type = UC_HOOK_INSN, this is the instruction ID.
          currently, only x86 in, out, syscall, sysenter, cpuid are supported.
@@ -603,7 +777,7 @@ uc_err uc_emu_stop(uc_engine *uc);
 */
 UNICORN_EXPORT
 uc_err uc_hook_add(uc_engine *uc, uc_hook *hh, int type, void *callback,
-        void *user_data, uint64_t begin, uint64_t end, ...);
+                   void *user_data, uint64_t begin, uint64_t end, ...);
 
 /*
  Unregister (remove) a hook callback.
@@ -621,11 +795,11 @@ UNICORN_EXPORT
 uc_err uc_hook_del(uc_engine *uc, uc_hook hh);
 
 typedef enum uc_prot {
-   UC_PROT_NONE = 0,
-   UC_PROT_READ = 1,
-   UC_PROT_WRITE = 2,
-   UC_PROT_EXEC = 4,
-   UC_PROT_ALL = 7,
+    UC_PROT_NONE = 0,
+    UC_PROT_READ = 1,
+    UC_PROT_WRITE = 2,
+    UC_PROT_EXEC = 4,
+    UC_PROT_ALL = 7,
 } uc_prot;
 
 /*
@@ -634,12 +808,14 @@ typedef enum uc_prot {
 
  @uc: handle returned by uc_open()
  @address: starting address of the new memory region to be mapped in.
-    This address must be aligned to 4KB, or this will return with UC_ERR_ARG error.
+    This address must be aligned to 4KB, or this will return with UC_ERR_ARG
+ error.
  @size: size of the new memory region to be mapped in.
-    This size must be a multiple of 4KB, or this will return with UC_ERR_ARG error.
+    This size must be a multiple of 4KB, or this will return with UC_ERR_ARG
+ error.
  @perms: Permissions for the newly mapped region.
-    This must be some combination of UC_PROT_READ | UC_PROT_WRITE | UC_PROT_EXEC,
-    or this will return with UC_ERR_ARG error.
+    This must be some combination of UC_PROT_READ | UC_PROT_WRITE |
+ UC_PROT_EXEC, or this will return with UC_ERR_ARG error.
 
  @return UC_ERR_OK on success, or other value on failure (refer to uc_err enum
    for detailed error).
@@ -653,21 +829,25 @@ uc_err uc_mem_map(uc_engine *uc, uint64_t address, size_t size, uint32_t perms);
 
  @uc: handle returned by uc_open()
  @address: starting address of the new memory region to be mapped in.
-    This address must be aligned to 4KB, or this will return with UC_ERR_ARG error.
+    This address must be aligned to 4KB, or this will return with UC_ERR_ARG
+ error.
  @size: size of the new memory region to be mapped in.
-    This size must be a multiple of 4KB, or this will return with UC_ERR_ARG error.
+    This size must be a multiple of 4KB, or this will return with UC_ERR_ARG
+ error.
  @perms: Permissions for the newly mapped region.
-    This must be some combination of UC_PROT_READ | UC_PROT_WRITE | UC_PROT_EXEC,
-    or this will return with UC_ERR_ARG error.
- @ptr: pointer to host memory backing the newly mapped memory. This host memory is
-    expected to be of equal or larger size than provided, and be mapped with at
-    least PROT_READ | PROT_WRITE. If it is not, the resulting behavior is undefined.
+    This must be some combination of UC_PROT_READ | UC_PROT_WRITE |
+ UC_PROT_EXEC, or this will return with UC_ERR_ARG error.
+ @ptr: pointer to host memory backing the newly mapped memory. This host memory
+ is expected to be an equal or larger size than provided, and be mapped with at
+    least PROT_READ | PROT_WRITE. If it is not, the resulting behavior is
+ undefined.
 
  @return UC_ERR_OK on success, or other value on failure (refer to uc_err enum
    for detailed error).
 */
 UNICORN_EXPORT
-uc_err uc_mem_map_ptr(uc_engine *uc, uint64_t address, size_t size, uint32_t perms, void *ptr);
+uc_err uc_mem_map_ptr(uc_engine *uc, uint64_t address, size_t size,
+                      uint32_t perms, void *ptr);
 
 /*
  Map MMIO in for emulation.
@@ -675,15 +855,16 @@ uc_err uc_mem_map_ptr(uc_engine *uc, uint64_t address, size_t size, uint32_t per
 
  @uc: handle returned by uc_open()
  @address: starting address of the new MMIO region to be mapped in.
-   This address must be aligned to 4KB, or this will return with UC_ERR_ARG error.
+   This address must be aligned to 4KB, or this will return with UC_ERR_ARG
+ error.
  @size: size of the new MMIO region to be mapped in.
    This size must be multiple of 4KB, or this will return with UC_ERR_ARG error.
  @read_cb: function for handling reads from this MMIO region.
- @user_data_read: user-defined data. This will be passed to @read_cb function in its
-   last argument @user_data
+ @user_data_read: user-defined data. This will be passed to @read_cb function in
+ its last argument @user_data
  @write_cb: function for handling writes to this MMIO region.
- @user_data_write: user-defined data. This will be passed to @write_cb function in its
-   last argument @user_data
+ @user_data_write: user-defined data. This will be passed to @write_cb function
+ in its last argument @user_data
  @return UC_ERR_OK on success, or other value on failure (refer to uc_err enum
    for detailed error).
  */
@@ -698,9 +879,11 @@ uc_err uc_mmio_map(uc_engine *uc, uint64_t address, size_t size,
 
  @uc: handle returned by uc_open()
  @address: starting address of the memory region to be unmapped.
-    This address must be aligned to 4KB, or this will return with UC_ERR_ARG error.
+    This address must be aligned to 4KB, or this will return with UC_ERR_ARG
+ error.
  @size: size of the memory region to be modified.
-    This size must be a multiple of 4KB, or this will return with UC_ERR_ARG error.
+    This size must be a multiple of 4KB, or this will return with UC_ERR_ARG
+ error.
 
  @return UC_ERR_OK on success, or other value on failure (refer to uc_err enum
    for detailed error).
@@ -714,18 +897,21 @@ uc_err uc_mem_unmap(uc_engine *uc, uint64_t address, size_t size);
 
  @uc: handle returned by uc_open()
  @address: starting address of the memory region to be modified.
-    This address must be aligned to 4KB, or this will return with UC_ERR_ARG error.
+    This address must be aligned to 4KB, or this will return with UC_ERR_ARG
+ error.
  @size: size of the memory region to be modified.
-    This size must be a multiple of 4KB, or this will return with UC_ERR_ARG error.
+    This size must be a multiple of 4KB, or this will return with UC_ERR_ARG
+ error.
  @perms: New permissions for the mapped region.
-    This must be some combination of UC_PROT_READ | UC_PROT_WRITE | UC_PROT_EXEC,
-    or this will return with UC_ERR_ARG error.
+    This must be some combination of UC_PROT_READ | UC_PROT_WRITE |
+ UC_PROT_EXEC, or this will return with UC_ERR_ARG error.
 
  @return UC_ERR_OK on success, or other value on failure (refer to uc_err enum
    for detailed error).
 */
 UNICORN_EXPORT
-uc_err uc_mem_protect(uc_engine *uc, uint64_t address, size_t size, uint32_t perms);
+uc_err uc_mem_protect(uc_engine *uc, uint64_t address, size_t size,
+                      uint32_t perms);
 
 /*
  Retrieve all memory regions mapped by uc_mem_map() and uc_mem_map_ptr()
@@ -763,9 +949,9 @@ uc_err uc_context_alloc(uc_engine *uc, uc_context **context);
 
 /*
  Free the memory allocated by uc_mem_regions.
- WARNING: After Unicorn 1.0.1rc5, the memory allocated by uc_context_alloc should
- be freed by uc_context_free(). Calling uc_free() may still work, but the result
- is **undefined**.
+ WARNING: After Unicorn 1.0.1rc5, the memory allocated by uc_context_alloc
+ should be freed by uc_context_free(). Calling uc_free() may still work, but
+ the result is **undefined**.
 
  @mem: memory allocated by uc_mem_regions (returned in *regions).
 
@@ -827,7 +1013,8 @@ uc_err uc_context_reg_read(uc_context *ctx, int regid, void *value);
    for detailed error).
 */
 UNICORN_EXPORT
-uc_err uc_context_reg_write_batch(uc_context *ctx, int *regs, void *const *vals, int count);
+uc_err uc_context_reg_write_batch(uc_context *ctx, int *regs, void *const *vals,
+                                  int count);
 
 /*
  Read multiple register values from a context.
@@ -841,7 +1028,8 @@ uc_err uc_context_reg_write_batch(uc_context *ctx, int *regs, void *const *vals,
    for detailed error).
 */
 UNICORN_EXPORT
-uc_err uc_context_reg_read_batch(uc_context *ctx, int *regs, void **vals, int count);
+uc_err uc_context_reg_read_batch(uc_context *ctx, int *regs, void **vals,
+                                 int count);
 
 /*
  Restore the current CPU context from a saved copy.
@@ -849,7 +1037,8 @@ uc_err uc_context_reg_read_batch(uc_context *ctx, int *regs, void **vals, int co
  state saved by uc_context_save().
 
  @uc: handle returned by uc_open()
- @context: handle returned by uc_context_alloc that has been used with uc_context_save
+ @context: handle returned by uc_context_alloc that has been used with
+ uc_context_save
 
  @return UC_ERR_OK on success, or other value on failure (refer to uc_err enum
    for detailed error).
@@ -857,10 +1046,9 @@ uc_err uc_context_reg_read_batch(uc_context *ctx, int *regs, void **vals, int co
 UNICORN_EXPORT
 uc_err uc_context_restore(uc_engine *uc, uc_context *context);
 
-
 /*
-  Return the size needed to store the cpu context. Can be used to allocate a buffer
-  to contain the cpu context and directly call uc_context_save.
+  Return the size needed to store the cpu context. Can be used to allocate a
+  buffer to contain the cpu context and directly call uc_context_save.
 
   @uc: handle returned by uc_open()
 
@@ -869,7 +1057,6 @@ uc_err uc_context_restore(uc_engine *uc, uc_context *context);
 UNICORN_EXPORT
 size_t uc_context_size(uc_engine *uc);
 
-
 /*
   Free the context allocated by uc_context_alloc().
 

include/unicorn/x86.h

@@ -13,17 +13,58 @@ extern "C" {
 
 #include "platform.h"
 
+typedef enum uc_cpu_x86 {
+    UC_CPU_X86_QEMU64 = 0,
+    UC_CPU_X86_PHENOM,
+    UC_CPU_X86_CORE2DUO,
+    UC_CPU_X86_KVM64,
+    UC_CPU_X86_QEMU32,
+    UC_CPU_X86_KVM32,
+    UC_CPU_X86_COREDUO,
+    UC_CPU_X86_486,
+    UC_CPU_X86_PENTIUM,
+    UC_CPU_X86_PENTIUM2,
+    UC_CPU_X86_PENTIUM3,
+    UC_CPU_X86_ATHLON,
+    UC_CPU_X86_N270,
+    UC_CPU_X86_CONROE,
+    UC_CPU_X86_PENRYN,
+    UC_CPU_X86_NEHALEM,
+    UC_CPU_X86_WESTMERE,
+    UC_CPU_X86_SANDYBRIDGE,
+    UC_CPU_X86_IVYBRIDGE,
+    UC_CPU_X86_HASWELL,
+    UC_CPU_X86_BROADWELL,
+    UC_CPU_X86_SKYLAKE_CLIENT,
+    UC_CPU_X86_SKYLAKE_SERVER,
+    UC_CPU_X86_CASCADELAKE_SERVER,
+    UC_CPU_X86_COOPERLAKE,
+    UC_CPU_X86_ICELAKE_CLIENT,
+    UC_CPU_X86_ICELAKE_SERVER,
+    UC_CPU_X86_DENVERTON,
+    UC_CPU_X86_SNOWRIDGE,
+    UC_CPU_X86_KNIGHTSMILL,
+    UC_CPU_X86_OPTERON_G1,
+    UC_CPU_X86_OPTERON_G2,
+    UC_CPU_X86_OPTERON_G3,
+    UC_CPU_X86_OPTERON_G4,
+    UC_CPU_X86_OPTERON_G5,
+    UC_CPU_X86_EPYC,
+    UC_CPU_X86_DHYANA,
+    UC_CPU_X86_EPYC_ROME
+} uc_cpu_x86;
+
 // Memory-Management Register for instructions IDTR, GDTR, LDTR, TR.
 // Borrow from SegmentCache in qemu/target-i386/cpu.h
 typedef struct uc_x86_mmr {
-    uint16_t selector;  /* not used by GDTR and IDTR */
-    uint64_t base;      /* handle 32 or 64 bit CPUs */
+    uint16_t selector; /* not used by GDTR and IDTR */
+    uint64_t base;     /* handle 32 or 64 bit CPUs */
     uint32_t limit;
-    uint32_t flags;     /* not used by GDTR and IDTR */
+    uint32_t flags; /* not used by GDTR and IDTR */
 } uc_x86_mmr;
 
-// Model-Specific Register structure, use this with UC_X86_REG_MSR (as the register ID) in
-// call to uc_reg_write/uc_reg_read() to manipulate MSRs.
+// Model-Specific Register structure, use this with UC_X86_REG_MSR (as the
+// register ID) in call to uc_reg_write/uc_reg_read() to manipulate MSRs.
 typedef struct uc_x86_msr {
     uint32_t rid;   // MSR id
     uint64_t value; // MSR value
@@ -35,62 +76,241 @@ typedef void (*uc_cb_insn_syscall_t)(struct uc_struct *uc, void *user_data);
 
 //> X86 registers
 typedef enum uc_x86_reg {
-	UC_X86_REG_INVALID = 0,
-	UC_X86_REG_AH, UC_X86_REG_AL, UC_X86_REG_AX, UC_X86_REG_BH, UC_X86_REG_BL,
-	UC_X86_REG_BP, UC_X86_REG_BPL, UC_X86_REG_BX, UC_X86_REG_CH, UC_X86_REG_CL,
-	UC_X86_REG_CS, UC_X86_REG_CX, UC_X86_REG_DH, UC_X86_REG_DI, UC_X86_REG_DIL,
-	UC_X86_REG_DL, UC_X86_REG_DS, UC_X86_REG_DX,  UC_X86_REG_EAX, UC_X86_REG_EBP,
-	UC_X86_REG_EBX, UC_X86_REG_ECX, UC_X86_REG_EDI, UC_X86_REG_EDX, UC_X86_REG_EFLAGS,
-	UC_X86_REG_EIP, UC_X86_REG_ES, UC_X86_REG_ESI, UC_X86_REG_ESP,
-	UC_X86_REG_FPSW, UC_X86_REG_FS, UC_X86_REG_GS, UC_X86_REG_IP, UC_X86_REG_RAX,
-	UC_X86_REG_RBP, UC_X86_REG_RBX, UC_X86_REG_RCX, UC_X86_REG_RDI, UC_X86_REG_RDX,
-	UC_X86_REG_RIP, UC_X86_REG_RSI, UC_X86_REG_RSP, UC_X86_REG_SI,
-	UC_X86_REG_SIL, UC_X86_REG_SP, UC_X86_REG_SPL, UC_X86_REG_SS, UC_X86_REG_CR0,
-	UC_X86_REG_CR1, UC_X86_REG_CR2, UC_X86_REG_CR3, UC_X86_REG_CR4, UC_X86_REG_CR8,
-	UC_X86_REG_DR0, UC_X86_REG_DR1, UC_X86_REG_DR2, UC_X86_REG_DR3, UC_X86_REG_DR4,
-	UC_X86_REG_DR5, UC_X86_REG_DR6, UC_X86_REG_DR7, UC_X86_REG_FP0, UC_X86_REG_FP1, 
-    UC_X86_REG_FP2, UC_X86_REG_FP3,
-	UC_X86_REG_FP4, UC_X86_REG_FP5, UC_X86_REG_FP6, UC_X86_REG_FP7,
-	UC_X86_REG_K0, UC_X86_REG_K1, UC_X86_REG_K2, UC_X86_REG_K3, UC_X86_REG_K4,
-	UC_X86_REG_K5, UC_X86_REG_K6, UC_X86_REG_K7, UC_X86_REG_MM0, UC_X86_REG_MM1,
-	UC_X86_REG_MM2, UC_X86_REG_MM3, UC_X86_REG_MM4, UC_X86_REG_MM5, UC_X86_REG_MM6,
-	UC_X86_REG_MM7, UC_X86_REG_R8, UC_X86_REG_R9, UC_X86_REG_R10, UC_X86_REG_R11,
-	UC_X86_REG_R12, UC_X86_REG_R13, UC_X86_REG_R14, UC_X86_REG_R15,
-	UC_X86_REG_ST0, UC_X86_REG_ST1, UC_X86_REG_ST2, UC_X86_REG_ST3,
-	UC_X86_REG_ST4, UC_X86_REG_ST5, UC_X86_REG_ST6, UC_X86_REG_ST7,
-	UC_X86_REG_XMM0, UC_X86_REG_XMM1, UC_X86_REG_XMM2, UC_X86_REG_XMM3, UC_X86_REG_XMM4,
-	UC_X86_REG_XMM5, UC_X86_REG_XMM6, UC_X86_REG_XMM7, UC_X86_REG_XMM8, UC_X86_REG_XMM9,
-	UC_X86_REG_XMM10, UC_X86_REG_XMM11, UC_X86_REG_XMM12, UC_X86_REG_XMM13, UC_X86_REG_XMM14,
-	UC_X86_REG_XMM15, UC_X86_REG_XMM16, UC_X86_REG_XMM17, UC_X86_REG_XMM18, UC_X86_REG_XMM19,
-	UC_X86_REG_XMM20, UC_X86_REG_XMM21, UC_X86_REG_XMM22, UC_X86_REG_XMM23, UC_X86_REG_XMM24,
-	UC_X86_REG_XMM25, UC_X86_REG_XMM26, UC_X86_REG_XMM27, UC_X86_REG_XMM28, UC_X86_REG_XMM29,
-	UC_X86_REG_XMM30, UC_X86_REG_XMM31, UC_X86_REG_YMM0, UC_X86_REG_YMM1, UC_X86_REG_YMM2,
-	UC_X86_REG_YMM3, UC_X86_REG_YMM4, UC_X86_REG_YMM5, UC_X86_REG_YMM6, UC_X86_REG_YMM7,
-	UC_X86_REG_YMM8, UC_X86_REG_YMM9, UC_X86_REG_YMM10, UC_X86_REG_YMM11, UC_X86_REG_YMM12,
-	UC_X86_REG_YMM13, UC_X86_REG_YMM14, UC_X86_REG_YMM15, UC_X86_REG_YMM16, UC_X86_REG_YMM17,
-	UC_X86_REG_YMM18, UC_X86_REG_YMM19, UC_X86_REG_YMM20, UC_X86_REG_YMM21, UC_X86_REG_YMM22,
-	UC_X86_REG_YMM23, UC_X86_REG_YMM24, UC_X86_REG_YMM25, UC_X86_REG_YMM26, UC_X86_REG_YMM27,
-	UC_X86_REG_YMM28, UC_X86_REG_YMM29, UC_X86_REG_YMM30, UC_X86_REG_YMM31, UC_X86_REG_ZMM0,
-	UC_X86_REG_ZMM1, UC_X86_REG_ZMM2, UC_X86_REG_ZMM3, UC_X86_REG_ZMM4, UC_X86_REG_ZMM5,
-	UC_X86_REG_ZMM6, UC_X86_REG_ZMM7, UC_X86_REG_ZMM8, UC_X86_REG_ZMM9, UC_X86_REG_ZMM10,
-	UC_X86_REG_ZMM11, UC_X86_REG_ZMM12, UC_X86_REG_ZMM13, UC_X86_REG_ZMM14, UC_X86_REG_ZMM15,
-	UC_X86_REG_ZMM16, UC_X86_REG_ZMM17, UC_X86_REG_ZMM18, UC_X86_REG_ZMM19, UC_X86_REG_ZMM20,
-	UC_X86_REG_ZMM21, UC_X86_REG_ZMM22, UC_X86_REG_ZMM23, UC_X86_REG_ZMM24, UC_X86_REG_ZMM25,
-	UC_X86_REG_ZMM26, UC_X86_REG_ZMM27, UC_X86_REG_ZMM28, UC_X86_REG_ZMM29, UC_X86_REG_ZMM30,
-	UC_X86_REG_ZMM31, UC_X86_REG_R8B, UC_X86_REG_R9B, UC_X86_REG_R10B, UC_X86_REG_R11B,
-	UC_X86_REG_R12B, UC_X86_REG_R13B, UC_X86_REG_R14B, UC_X86_REG_R15B, UC_X86_REG_R8D,
-	UC_X86_REG_R9D, UC_X86_REG_R10D, UC_X86_REG_R11D, UC_X86_REG_R12D, UC_X86_REG_R13D,
-	UC_X86_REG_R14D, UC_X86_REG_R15D, UC_X86_REG_R8W, UC_X86_REG_R9W, UC_X86_REG_R10W,
-	UC_X86_REG_R11W, UC_X86_REG_R12W, UC_X86_REG_R13W, UC_X86_REG_R14W, UC_X86_REG_R15W,
-	UC_X86_REG_IDTR, UC_X86_REG_GDTR, UC_X86_REG_LDTR, UC_X86_REG_TR, UC_X86_REG_FPCW,
-	UC_X86_REG_FPTAG,
+    UC_X86_REG_INVALID = 0,
+    UC_X86_REG_AH,
+    UC_X86_REG_AL,
+    UC_X86_REG_AX,
+    UC_X86_REG_BH,
+    UC_X86_REG_BL,
+    UC_X86_REG_BP,
+    UC_X86_REG_BPL,
+    UC_X86_REG_BX,
+    UC_X86_REG_CH,
+    UC_X86_REG_CL,
+    UC_X86_REG_CS,
+    UC_X86_REG_CX,
+    UC_X86_REG_DH,
+    UC_X86_REG_DI,
+    UC_X86_REG_DIL,
+    UC_X86_REG_DL,
+    UC_X86_REG_DS,
+    UC_X86_REG_DX,
+    UC_X86_REG_EAX,
+    UC_X86_REG_EBP,
+    UC_X86_REG_EBX,
+    UC_X86_REG_ECX,
+    UC_X86_REG_EDI,
+    UC_X86_REG_EDX,
+    UC_X86_REG_EFLAGS,
+    UC_X86_REG_EIP,
+    UC_X86_REG_ES,
+    UC_X86_REG_ESI,
+    UC_X86_REG_ESP,
+    UC_X86_REG_FPSW,
+    UC_X86_REG_FS,
+    UC_X86_REG_GS,
+    UC_X86_REG_IP,
+    UC_X86_REG_RAX,
+    UC_X86_REG_RBP,
+    UC_X86_REG_RBX,
+    UC_X86_REG_RCX,
+    UC_X86_REG_RDI,
+    UC_X86_REG_RDX,
+    UC_X86_REG_RIP,
+    UC_X86_REG_RSI,
+    UC_X86_REG_RSP,
+    UC_X86_REG_SI,
+    UC_X86_REG_SIL,
+    UC_X86_REG_SP,
+    UC_X86_REG_SPL,
+    UC_X86_REG_SS,
+    UC_X86_REG_CR0,
+    UC_X86_REG_CR1,
+    UC_X86_REG_CR2,
+    UC_X86_REG_CR3,
+    UC_X86_REG_CR4,
+    UC_X86_REG_CR8,
+    UC_X86_REG_DR0,
+    UC_X86_REG_DR1,
+    UC_X86_REG_DR2,
+    UC_X86_REG_DR3,
+    UC_X86_REG_DR4,
+    UC_X86_REG_DR5,
+    UC_X86_REG_DR6,
+    UC_X86_REG_DR7,
+    UC_X86_REG_FP0,
+    UC_X86_REG_FP1,
+    UC_X86_REG_FP2,
+    UC_X86_REG_FP3,
+    UC_X86_REG_FP4,
+    UC_X86_REG_FP5,
+    UC_X86_REG_FP6,
+    UC_X86_REG_FP7,
+    UC_X86_REG_K0,
+    UC_X86_REG_K1,
+    UC_X86_REG_K2,
+    UC_X86_REG_K3,
+    UC_X86_REG_K4,
+    UC_X86_REG_K5,
+    UC_X86_REG_K6,
+    UC_X86_REG_K7,
+    UC_X86_REG_MM0,
+    UC_X86_REG_MM1,
+    UC_X86_REG_MM2,
+    UC_X86_REG_MM3,
+    UC_X86_REG_MM4,
+    UC_X86_REG_MM5,
+    UC_X86_REG_MM6,
+    UC_X86_REG_MM7,
+    UC_X86_REG_R8,
+    UC_X86_REG_R9,
+    UC_X86_REG_R10,
+    UC_X86_REG_R11,
+    UC_X86_REG_R12,
+    UC_X86_REG_R13,
+    UC_X86_REG_R14,
+    UC_X86_REG_R15,
+    UC_X86_REG_ST0,
+    UC_X86_REG_ST1,
+    UC_X86_REG_ST2,
+    UC_X86_REG_ST3,
+    UC_X86_REG_ST4,
+    UC_X86_REG_ST5,
+    UC_X86_REG_ST6,
+    UC_X86_REG_ST7,
+    UC_X86_REG_XMM0,
+    UC_X86_REG_XMM1,
+    UC_X86_REG_XMM2,
+    UC_X86_REG_XMM3,
+    UC_X86_REG_XMM4,
+    UC_X86_REG_XMM5,
+    UC_X86_REG_XMM6,
+    UC_X86_REG_XMM7,
+    UC_X86_REG_XMM8,
+    UC_X86_REG_XMM9,
+    UC_X86_REG_XMM10,
+    UC_X86_REG_XMM11,
+    UC_X86_REG_XMM12,
+    UC_X86_REG_XMM13,
+    UC_X86_REG_XMM14,
+    UC_X86_REG_XMM15,
+    UC_X86_REG_XMM16,
+    UC_X86_REG_XMM17,
+    UC_X86_REG_XMM18,
+    UC_X86_REG_XMM19,
+    UC_X86_REG_XMM20,
+    UC_X86_REG_XMM21,
+    UC_X86_REG_XMM22,
+    UC_X86_REG_XMM23,
+    UC_X86_REG_XMM24,
+    UC_X86_REG_XMM25,
+    UC_X86_REG_XMM26,
+    UC_X86_REG_XMM27,
+    UC_X86_REG_XMM28,
+    UC_X86_REG_XMM29,
+    UC_X86_REG_XMM30,
+    UC_X86_REG_XMM31,
+    UC_X86_REG_YMM0,
+    UC_X86_REG_YMM1,
+    UC_X86_REG_YMM2,
+    UC_X86_REG_YMM3,
+    UC_X86_REG_YMM4,
+    UC_X86_REG_YMM5,
+    UC_X86_REG_YMM6,
+    UC_X86_REG_YMM7,
+    UC_X86_REG_YMM8,
+    UC_X86_REG_YMM9,
+    UC_X86_REG_YMM10,
+    UC_X86_REG_YMM11,
+    UC_X86_REG_YMM12,
+    UC_X86_REG_YMM13,
+    UC_X86_REG_YMM14,
+    UC_X86_REG_YMM15,
+    UC_X86_REG_YMM16,
+    UC_X86_REG_YMM17,
+    UC_X86_REG_YMM18,
+    UC_X86_REG_YMM19,
+    UC_X86_REG_YMM20,
+    UC_X86_REG_YMM21,
+    UC_X86_REG_YMM22,
+    UC_X86_REG_YMM23,
+    UC_X86_REG_YMM24,
+    UC_X86_REG_YMM25,
+    UC_X86_REG_YMM26,
+    UC_X86_REG_YMM27,
+    UC_X86_REG_YMM28,
+    UC_X86_REG_YMM29,
+    UC_X86_REG_YMM30,
+    UC_X86_REG_YMM31,
+    UC_X86_REG_ZMM0,
+    UC_X86_REG_ZMM1,
+    UC_X86_REG_ZMM2,
+    UC_X86_REG_ZMM3,
+    UC_X86_REG_ZMM4,
+    UC_X86_REG_ZMM5,
+    UC_X86_REG_ZMM6,
+    UC_X86_REG_ZMM7,
+    UC_X86_REG_ZMM8,
+    UC_X86_REG_ZMM9,
+    UC_X86_REG_ZMM10,
+    UC_X86_REG_ZMM11,
+    UC_X86_REG_ZMM12,
+    UC_X86_REG_ZMM13,
+    UC_X86_REG_ZMM14,
+    UC_X86_REG_ZMM15,
+    UC_X86_REG_ZMM16,
+    UC_X86_REG_ZMM17,
+    UC_X86_REG_ZMM18,
+    UC_X86_REG_ZMM19,
+    UC_X86_REG_ZMM20,
+    UC_X86_REG_ZMM21,
+    UC_X86_REG_ZMM22,
+    UC_X86_REG_ZMM23,
+    UC_X86_REG_ZMM24,
+    UC_X86_REG_ZMM25,
+    UC_X86_REG_ZMM26,
+    UC_X86_REG_ZMM27,
+    UC_X86_REG_ZMM28,
+    UC_X86_REG_ZMM29,
+    UC_X86_REG_ZMM30,
+    UC_X86_REG_ZMM31,
+    UC_X86_REG_R8B,
+    UC_X86_REG_R9B,
+    UC_X86_REG_R10B,
+    UC_X86_REG_R11B,
+    UC_X86_REG_R12B,
+    UC_X86_REG_R13B,
+    UC_X86_REG_R14B,
+    UC_X86_REG_R15B,
+    UC_X86_REG_R8D,
+    UC_X86_REG_R9D,
+    UC_X86_REG_R10D,
+    UC_X86_REG_R11D,
+    UC_X86_REG_R12D,
+    UC_X86_REG_R13D,
+    UC_X86_REG_R14D,
+    UC_X86_REG_R15D,
+    UC_X86_REG_R8W,
+    UC_X86_REG_R9W,
+    UC_X86_REG_R10W,
+    UC_X86_REG_R11W,
+    UC_X86_REG_R12W,
+    UC_X86_REG_R13W,
+    UC_X86_REG_R14W,
+    UC_X86_REG_R15W,
+    UC_X86_REG_IDTR,
+    UC_X86_REG_GDTR,
+    UC_X86_REG_LDTR,
+    UC_X86_REG_TR,
+    UC_X86_REG_FPCW,
+    UC_X86_REG_FPTAG,
     UC_X86_REG_MSR, // Model-Specific Register
     UC_X86_REG_MXCSR,
     UC_X86_REG_FS_BASE, // Base regs for x86_64
     UC_X86_REG_GS_BASE,
     UC_X86_REG_FLAGS,
     UC_X86_REG_RFLAGS,
-    UC_X86_REG_ENDING		// <-- mark the end of the list of registers
+    UC_X86_REG_ENDING // <-- mark the end of the list of registers
 } uc_x86_reg;
 
 //> X86 instructions

qemu/aarch64.h

@@ -4,6 +4,7 @@
 #ifndef UNICORN_ARCH_POSTFIX
 #define UNICORN_ARCH_POSTFIX _aarch64
 #endif
+#define tb_invalidate_phys_range tb_invalidate_phys_range_aarch64
 #define use_idiv_instructions use_idiv_instructions_aarch64
 #define arm_arch arm_arch_aarch64
 #define tb_target_set_jmp_target tb_target_set_jmp_target_aarch64

qemu/aarch64eb.h

@@ -4,6 +4,7 @@
 #ifndef UNICORN_ARCH_POSTFIX
 #define UNICORN_ARCH_POSTFIX _aarch64eb
 #endif
+#define tb_invalidate_phys_range tb_invalidate_phys_range_aarch64eb
 #define use_idiv_instructions use_idiv_instructions_aarch64eb
 #define arm_arch arm_arch_aarch64eb
 #define tb_target_set_jmp_target tb_target_set_jmp_target_aarch64eb

qemu/accel/tcg/cpu-exec.c

@@ -245,6 +245,10 @@ static inline TranslationBlock *tb_find(CPUState *cpu,
     TranslationBlock *tb;
     target_ulong cs_base, pc;
     uint32_t flags;
+    uc_tb cur_tb, prev_tb;
+    uc_engine *uc = cpu->uc;
+    struct list_item *cur;
+    struct hook *hook;
 
     tb = tb_lookup__cpu_state(cpu, &pc, &cs_base, &flags, cf_mask);
     if (tb == NULL) {
@@ -265,6 +269,23 @@ static inline TranslationBlock *tb_find(CPUState *cpu,
     if (last_tb) {
         tb_add_jump(last_tb, tb_exit, tb);
     }
+
+    UC_TB_COPY(&cur_tb, tb);
+
+    if (last_tb) {
+        UC_TB_COPY(&prev_tb, last_tb);
+        for (cur = uc->hook[UC_HOOK_EDGE_GENERATED_IDX].head;
+            cur != NULL && (hook = (struct hook *)cur->data); cur = cur->next) {
+            if (hook->to_delete) {
+                continue;
+            }
+
+            if (HOOK_BOUND_CHECK(hook, (uint64_t)tb->pc)) {
+                ((uc_hook_edge_gen_t)hook->callback)(uc, &cur_tb, &prev_tb, hook->user_data);
+            }
+        }
+    }
+
     return tb;
 }
 

qemu/accel/tcg/translate-all.c

@@ -980,6 +980,81 @@ static void tb_htable_init(struct uc_struct *uc)
     qht_init(&uc->tcg_ctx->tb_ctx.htable, tb_cmp, CODE_GEN_HTABLE_SIZE, mode);
 }
 
+
+static void uc_invalidate_tb(struct uc_struct *uc, uint64_t start_addr, size_t len) 
+{
+    tb_page_addr_t start, end;
+
+    // GVA to GPA (GPA -> HVA via page_find, HVA->HPA via host mmu)
+    start = get_page_addr_code(uc->cpu->env_ptr, start_addr) & (target_ulong)(-1);
+    
+    // For 32bit target.
+    end = (start + len) & (target_ulong)(-1);
+
+    // We get a wrap?
+    if (start > end) {
+        return;
+    }
+
+    tb_invalidate_phys_range(uc, start, end);
+}
+
+static uc_err uc_gen_tb(struct uc_struct *uc, uint64_t addr, uc_tb *out_tb) 
+{
+    TranslationBlock *tb;
+    target_ulong cs_base, pc;
+    CPUState *cpu = uc->cpu;
+    CPUArchState *env = (CPUArchState *)cpu->env_ptr;
+    uint32_t flags;
+    uint32_t hash;
+    uint32_t cflags = cpu->cflags_next_tb;
+
+    if (cflags == -1) {
+        cflags = curr_cflags();
+    }
+
+    cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
+
+    // Unicorn: Our hack here.
+    pc = addr;
+
+    hash = tb_jmp_cache_hash_func(env->uc, pc);
+    tb = cpu->tb_jmp_cache[hash];
+
+    cflags &= ~CF_CLUSTER_MASK;
+    cflags |= cpu->cluster_index << CF_CLUSTER_SHIFT;
+
+    if (unlikely(!(tb &&
+                   tb->pc == pc &&
+                   tb->cs_base == cs_base &&
+                   tb->flags == flags &&
+                   tb->trace_vcpu_dstate == *cpu->trace_dstate &&
+                   (tb_cflags(tb) & (CF_HASH_MASK | CF_INVALID)) == cflags))) {
+
+        tb = tb_htable_lookup(cpu, pc, cs_base, flags, cflags);
+        cpu->tb_jmp_cache[hash] = tb;
+
+        if (tb == NULL) {
+            mmap_lock();
+            tb = tb_gen_code(cpu, pc, cs_base, flags, cflags);
+            mmap_unlock();
+            /* We add the TB in the virtual pc hash table for the fast lookup */
+            cpu->tb_jmp_cache[hash] = tb;
+        }
+    }
+
+    // If we still couldn't generate a TB, it must be out of memory.
+    if (tb == NULL) {
+        return UC_ERR_NOMEM;
+    }
+
+    if (out_tb != NULL) {
+        UC_TB_COPY(out_tb, tb);
+    }
+
+    return UC_ERR_OK;
+}
+
 /* Must be called before using the QEMU cpus. 'tb_size' is the size
    (in bytes) allocated to the translation buffer. Zero means default
    size. */
@@ -1000,6 +1075,9 @@ void tcg_exec_init(struct uc_struct *uc, unsigned long tb_size)
     tcg_prologue_init(uc->tcg_ctx);
     /* cpu_interrupt_handler is not used in uc1 */
     uc->l1_map = g_malloc0(sizeof(void *) * V_L1_MAX_SIZE);
+    /* Invalidate / Cache TBs */
+    uc->uc_invalidate_tb = uc_invalidate_tb;
+    uc->uc_gen_tb = uc_gen_tb;
 }
 
 /* call with @p->lock held */
@@ -1753,7 +1831,8 @@ void tb_invalidate_phys_range(struct uc_struct *uc, ram_addr_t start, ram_addr_t
 
     pages = page_collection_lock(uc, start, end);
     for (next = (start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
-         start < end;
+         //start < end; Unicorn: Fix possible wrap around
+         (intptr_t)(end - start) > 0;
          start = next, next += TARGET_PAGE_SIZE) {
         PageDesc *pd = page_find(uc, start >> TARGET_PAGE_BITS);
         tb_page_addr_t bound = MIN(next, end);

qemu/accel/tcg/translate-all.h

@@ -30,6 +30,7 @@ void tb_invalidate_phys_page_fast(struct uc_struct *uc, struct page_collection *
                                   tb_page_addr_t start, int len,
                                   uintptr_t retaddr);
 void tb_invalidate_phys_page_range(struct uc_struct *uc, tb_page_addr_t start, tb_page_addr_t end);
+void tb_invalidate_phys_range(struct uc_struct *uc, ram_addr_t start, ram_addr_t end);
 void tb_check_watchpoint(CPUState *cpu, uintptr_t retaddr);
 
 #endif /* TRANSLATE_ALL_H */

qemu/accel/tcg/translator.c

@@ -58,7 +58,7 @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
 
     /* Unicorn: early check to see if the address of this block is
      * the "run until" address. */
-    if (tb->pc == cpu->uc->addr_end) {
+    if (uc_addr_is_exit(uc, tb->pc)) {
         // This should catch that instruction is at the end
         // and generate appropriate halting code.
         gen_tb_start(tcg_ctx, db->tb);

qemu/arm.h

@@ -4,6 +4,7 @@
 #ifndef UNICORN_ARCH_POSTFIX
 #define UNICORN_ARCH_POSTFIX _arm
 #endif
+#define tb_invalidate_phys_range tb_invalidate_phys_range_arm
 #define use_idiv_instructions use_idiv_instructions_arm
 #define arm_arch arm_arch_arm
 #define tb_target_set_jmp_target tb_target_set_jmp_target_arm

qemu/armeb.h

@@ -4,6 +4,7 @@
 #ifndef UNICORN_ARCH_POSTFIX
 #define UNICORN_ARCH_POSTFIX _armeb
 #endif
+#define tb_invalidate_phys_range tb_invalidate_phys_range_armeb
 #define use_idiv_instructions use_idiv_instructions_armeb
 #define arm_arch arm_arch_armeb
 #define tb_target_set_jmp_target tb_target_set_jmp_target_armeb

qemu/m68k.h

@@ -4,6 +4,7 @@
 #ifndef UNICORN_ARCH_POSTFIX
 #define UNICORN_ARCH_POSTFIX _m68k
 #endif
+#define tb_invalidate_phys_range tb_invalidate_phys_range_m68k
 #define use_idiv_instructions use_idiv_instructions_m68k
 #define arm_arch arm_arch_m68k
 #define tb_target_set_jmp_target tb_target_set_jmp_target_m68k

qemu/mips.h

@@ -4,6 +4,7 @@
 #ifndef UNICORN_ARCH_POSTFIX
 #define UNICORN_ARCH_POSTFIX _mips
 #endif
+#define tb_invalidate_phys_range tb_invalidate_phys_range_mips
 #define use_idiv_instructions use_idiv_instructions_mips
 #define arm_arch arm_arch_mips
 #define tb_target_set_jmp_target tb_target_set_jmp_target_mips

qemu/mips64.h

@@ -4,6 +4,7 @@
 #ifndef UNICORN_ARCH_POSTFIX
 #define UNICORN_ARCH_POSTFIX _mips64
 #endif
+#define tb_invalidate_phys_range tb_invalidate_phys_range_mips64
 #define use_idiv_instructions use_idiv_instructions_mips64
 #define arm_arch arm_arch_mips64
 #define tb_target_set_jmp_target tb_target_set_jmp_target_mips64

qemu/mips64el.h

@@ -4,6 +4,7 @@
 #ifndef UNICORN_ARCH_POSTFIX
 #define UNICORN_ARCH_POSTFIX _mips64el
 #endif
+#define tb_invalidate_phys_range tb_invalidate_phys_range_mips64el
 #define use_idiv_instructions use_idiv_instructions_mips64el
 #define arm_arch arm_arch_mips64el
 #define tb_target_set_jmp_target tb_target_set_jmp_target_mips64el

qemu/mipsel.h

@@ -4,6 +4,7 @@
 #ifndef UNICORN_ARCH_POSTFIX
 #define UNICORN_ARCH_POSTFIX _mipsel
 #endif
+#define tb_invalidate_phys_range tb_invalidate_phys_range_mipsel
 #define use_idiv_instructions use_idiv_instructions_mipsel
 #define arm_arch arm_arch_mipsel
 #define tb_target_set_jmp_target tb_target_set_jmp_target_mipsel

qemu/ppc.h

@@ -4,6 +4,7 @@
 #ifndef UNICORN_ARCH_POSTFIX
 #define UNICORN_ARCH_POSTFIX _ppc
 #endif
+#define tb_invalidate_phys_range tb_invalidate_phys_range_ppc
 #define use_idiv_instructions use_idiv_instructions_ppc
 #define arm_arch arm_arch_ppc
 #define tb_target_set_jmp_target tb_target_set_jmp_target_ppc

qemu/ppc64.h

@@ -4,6 +4,7 @@
 #ifndef UNICORN_ARCH_POSTFIX
 #define UNICORN_ARCH_POSTFIX _ppc64
 #endif
+#define tb_invalidate_phys_range tb_invalidate_phys_range_ppc64
 #define use_idiv_instructions use_idiv_instructions_ppc64
 #define arm_arch arm_arch_ppc64
 #define tb_target_set_jmp_target tb_target_set_jmp_target_ppc64

qemu/riscv32.h

@@ -4,6 +4,7 @@
 #ifndef UNICORN_ARCH_POSTFIX
 #define UNICORN_ARCH_POSTFIX _riscv32
 #endif
+#define tb_invalidate_phys_range tb_invalidate_phys_range_riscv32
 #define use_idiv_instructions use_idiv_instructions_riscv32
 #define arm_arch arm_arch_riscv32
 #define tb_target_set_jmp_target tb_target_set_jmp_target_riscv32

qemu/riscv64.h

@@ -4,6 +4,7 @@
 #ifndef UNICORN_ARCH_POSTFIX
 #define UNICORN_ARCH_POSTFIX _riscv64
 #endif
+#define tb_invalidate_phys_range tb_invalidate_phys_range_riscv64
 #define use_idiv_instructions use_idiv_instructions_riscv64
 #define arm_arch arm_arch_riscv64
 #define tb_target_set_jmp_target tb_target_set_jmp_target_riscv64

qemu/softmmu/cpus.c

@@ -27,6 +27,7 @@
 #include "qemu/bitmap.h"
 #include "tcg/tcg.h"
 #include "exec/tb-hash.h"
+#include "accel/tcg/translate-all.h"
 
 #include "uc_priv.h"
 
@@ -170,6 +171,28 @@ void cpu_stop_current(struct uc_struct *uc)
     }
 }
 
+
+
+static inline gboolean uc_exit_invalidate_iter(gpointer key, gpointer val, gpointer data) 
+{
+    uint64_t exit = *((uint64_t*)key);
+    uc_engine *uc = (uc_engine*)data;
+    
+    if (exit != 0) {
+        // Unicorn: Why addr - 1?
+        // 
+        // 0: INC ecx
+        // 1: DEC edx <--- We put exit here, then the range of TB is [0, 1)
+        //
+        // While tb_invalidate_phys_range invalides [start, end)
+        //
+        // This function is designed to used with g_tree_foreach
+        uc->uc_invalidate_tb(uc, exit - 1, 1);
+    }
+
+    return false;
+}
+
 void resume_all_vcpus(struct uc_struct* uc)
 {
     CPUState *cpu = uc->cpu;
@@ -185,15 +208,11 @@ void resume_all_vcpus(struct uc_struct* uc)
         }
     }
 
-    // clear the cache of the addr_end address, since the generated code
+    // clear the cache of the exits address, since the generated code
     // at that address is to exit emulation, but not for the instruction there.
     // if we dont do this, next time we cannot emulate at that address
-    TranslationBlock *tb = cpu->tb_jmp_cache[tb_jmp_cache_hash_func(uc, uc->addr_end)];
-    if (tb) {
-        qht_remove(&uc->tcg_ctx->tb_ctx.htable, tb, tb->hash);
-        tb_flush_jmp_cache(cpu, uc->addr_end);
-    }
 
+    g_tree_foreach(uc->exits, uc_exit_invalidate_iter, (void*)uc);
 
     cpu->created = false;
 }

qemu/sparc.h

@@ -4,6 +4,7 @@
 #ifndef UNICORN_ARCH_POSTFIX
 #define UNICORN_ARCH_POSTFIX _sparc
 #endif
+#define tb_invalidate_phys_range tb_invalidate_phys_range_sparc
 #define use_idiv_instructions use_idiv_instructions_sparc
 #define arm_arch arm_arch_sparc
 #define tb_target_set_jmp_target tb_target_set_jmp_target_sparc

qemu/sparc64.h

@@ -4,6 +4,7 @@
 #ifndef UNICORN_ARCH_POSTFIX
 #define UNICORN_ARCH_POSTFIX _sparc64
 #endif
+#define tb_invalidate_phys_range tb_invalidate_phys_range_sparc64
 #define use_idiv_instructions use_idiv_instructions_sparc64
 #define arm_arch arm_arch_sparc64
 #define tb_target_set_jmp_target tb_target_set_jmp_target_sparc64