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set pc_start on disasm

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mio
2025-02-10 21:28:23 +08:00
parent 904efc16c0
commit 2619b12cf0
1 changed files with 2 additions and 1 deletions
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3
qemu/target/arm/translate.c
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@@ -452,7 +452,7 @@ static void gen_sub_carry(TCGContext *tcg_ctx, TCGv_i32 dest, TCGv_i32 t0, TCGv_
tcg_gen_subi_i32(tcg_ctx, dest, dest, 1); tcg_gen_subi_i32(tcg_ctx, dest, dest, 1);
} }
static inline void mb_tcg_opcode_cmp_hook(TCGContext *tcg_ctx, TCGv_i64 v0, TCGv_i64 v1, uint32_t size) static inline void mb_tcg_opcode_cmp_hook(TCGContext *tcg_ctx, TCGv_i64 v0, TCGv_i64 v1, uint32_t size, uint32_t pc)
{ {
uc_engine *uc = tcg_ctx->uc; uc_engine *uc = tcg_ctx->uc;
if (HOOK_EXISTS_BOUNDED(uc, UC_HOOK_TCG_OPCODE, tcg_ctx->pc_start)) { if (HOOK_EXISTS_BOUNDED(uc, UC_HOOK_TCG_OPCODE, tcg_ctx->pc_start)) {
@@ -10925,6 +10925,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
{ {
unsigned int cond = insn >> 28; unsigned int cond = insn >> 28;
TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGContext *tcg_ctx = s->uc->tcg_ctx;
tcg_ctx->pc_start = s->pc_curr;
/* M variants do not implement ARM mode; this must raise the INVSTATE /* M variants do not implement ARM mode; this must raise the INVSTATE
* UsageFault exception. * UsageFault exception.