9cfd5cfac3
- Added fullMode input in workflow_dispatch
- Take decision whether to build either in debug or release mode and if to build for all python versions according to the commit message patterns
- Set proper artifact names
- Removed not needed steps
- Compacted some steps in order to leverage more the matrix feature
- Bumped cibuildwheel action to 2.22.0
- Run actual regress tests in place of sample scripts
- Specify optional test install in pyproject.toml with proper requirements
- Derive package version from git tags
- Add GENERATORS env var support in setup.py to specify cmake generator and minor refactoring
- Minor cleanup/refactoring for the regress test suite
- Marked some regress tests with skipIf to skip them in case of old python versions
- Marked some failing regress tests to be checked with skipIf
137 lines
4.1 KiB
Python
Executable File
137 lines
4.1 KiB
Python
Executable File
#!/usr/bin/env python
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# Sample code for Unicorn.
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# By Lazymio(@wtdcode), 2021
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from unicorn import *
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from unicorn.x86_const import *
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from datetime import datetime
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def test_uc_ctl_read():
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uc = Uc(UC_ARCH_X86, UC_MODE_32)
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print("Reading some properties by uc_ctl.")
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arch = uc.ctl_get_arch()
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mode = uc.ctl_get_mode()
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page_size = uc.ctl_get_page_size()
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timeout = uc.ctl_get_timeout()
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print(">>> arch={arch} mode={mode} page size={page_size} timeout={timeout}".format(arch=arch, mode=mode,
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page_size=page_size,
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timeout=timeout))
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def time_emulation(uc, start, end):
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n = datetime.now()
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uc.emu_start(start, end)
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return (datetime.now() - n).total_seconds() * 1e6
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# TODO: Check if worth adapting the ctl_request_cache method for py2 bindings
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def test_uc_ctl_tb_cache():
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# Initialize emulator in X86-32bit mode
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uc = Uc(UC_ARCH_X86, UC_MODE_32)
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addr = 0x10000
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# Fill the code buffer with NOP.
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code = b"\x90" * 8 * 512
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print("Controlling the TB cache in a finer granularity by uc_ctl.")
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uc.mem_map(addr, 0x10000)
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# Write our code to the memory.
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uc.mem_write(addr, code)
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# Do emulation without any cache.
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standard = time_emulation(uc, addr, addr + len(code))
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# Now we request cache for all TBs.
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for i in range(8):
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tb = uc.ctl_request_cache(addr + i * 512)
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print(">>> TB is cached at {:#x} which has {} instructions with {} bytes".format(tb[0], tb[1], tb[2]))
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# Do emulation with all TB cached.
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cached = time_emulation(uc, addr, addr + len(code))
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# Now we clear cache for all TBs.
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for i in range(8):
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uc.ctl_remove_cache(addr + i * 512, addr + i * 512 + 1)
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evicted = time_emulation(uc, addr, addr + len(code))
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print(">>> Run time: First time {standard}, Cached: {cached}, Cached evicted: {evicted}".format(standard=standard,
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cached=cached,
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evicted=evicted))
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def trace_new_edge(uc, cur, prev, data):
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print(">>> Getting a new edge from {:#x} to {:#x}".format(prev.pc + prev.size - 1, cur.pc))
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def trace_tcg_sub(uc, address, arg1, arg2, size, data):
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print(">>> Get a tcg sub opcode at {address:#x} with args: {arg1} and {arg2}".format(address=address, arg1=arg1,
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arg2=arg2))
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# TODO: Check if worth adapting the hook_add method for py2 bindings
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def test_uc_ctl_exits():
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uc = Uc(UC_ARCH_X86, UC_MODE_32)
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addr = 0x1000
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# cmp eax, 0;
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# jg lb;
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# inc eax;
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# nop;
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# lb:
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# inc ebx;
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# nop;
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code = b"\x83\xf8\x00\x7f\x02\x40\x90\x43\x90"
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exits = [addr + 6, addr + 8]
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print("Using multiple exits by uc_ctl")
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uc.mem_map(addr, 0x1000)
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# Write our code to the memory.
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uc.mem_write(addr, code)
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# We trace if any new edge is generated.
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uc.hook_add(UC_HOOK_EDGE_GENERATED, trace_new_edge)
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# Trace cmp instruction.
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uc.hook_add(UC_HOOK_TCG_OPCODE, trace_tcg_sub, aux1=UC_TCG_OP_SUB, aux2=UC_TCG_OP_FLAG_CMP)
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uc.ctl_exits_enabled(True)
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uc.ctl_set_exits(exits)
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# This should stop at ADDRESS + 6 and increase eax, even though we don't provide an exit.
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uc.emu_start(addr, 0)
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eax = uc.reg_read(UC_X86_REG_EAX)
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ebx = uc.reg_read(UC_X86_REG_EBX)
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print(">>> eax = {eax:#x} and ebx = {ebx:#x} after the first emulation".format(eax=eax, ebx=ebx))
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# This should stop at ADDRESS + 8, even though we don't provide an exit.
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uc.emu_start(addr, 0)
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eax = uc.reg_read(UC_X86_REG_EAX)
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ebx = uc.reg_read(UC_X86_REG_EBX)
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print(">>> eax = {eax:#x} and ebx = {ebx:#x} after the first emulation".format(eax=eax, ebx=ebx))
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if __name__ == "__main__":
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test_uc_ctl_read()
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print("=" * 32)
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test_uc_ctl_tb_cache()
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print("=" * 32)
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test_uc_ctl_exits()
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