9cfd5cfac3
- Added fullMode input in workflow_dispatch
- Take decision whether to build either in debug or release mode and if to build for all python versions according to the commit message patterns
- Set proper artifact names
- Removed not needed steps
- Compacted some steps in order to leverage more the matrix feature
- Bumped cibuildwheel action to 2.22.0
- Run actual regress tests in place of sample scripts
- Specify optional test install in pyproject.toml with proper requirements
- Derive package version from git tags
- Add GENERATORS env var support in setup.py to specify cmake generator and minor refactoring
- Minor cleanup/refactoring for the regress test suite
- Marked some regress tests with skipIf to skip them in case of old python versions
- Marked some failing regress tests to be checked with skipIf
93 lines
2.8 KiB
Python
Executable File
93 lines
2.8 KiB
Python
Executable File
# By Mariano Graziano
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import platform
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import regress
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import struct
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import unittest
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from unicorn import *
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from unicorn.x86_const import *
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class Emulator:
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def __init__(self, code, stack):
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def __page_aligned(address):
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return address & ~(0x1000 - 1)
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self.unicorn_code = code
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self.unicorn_stack = stack
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self.mu = Uc(UC_ARCH_X86, UC_MODE_64)
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regress.logger.debug("mapping code : %#x", __page_aligned(code))
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regress.logger.debug("mapping stack : %#x", __page_aligned(stack))
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self.mu.mem_map(__page_aligned(code), 0x1000)
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self.mu.mem_map(__page_aligned(stack), 0x1000)
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self.mu.reg_write(UC_X86_REG_RSP, stack)
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self.mu.reg_write(UC_X86_REG_RIP, code)
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self.set_hooks()
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def set_hooks(self):
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self.mu.hook_add(UC_HOOK_MEM_WRITE, self.hook_mem_access)
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self.mu.hook_add(UC_HOOK_MEM_READ_UNMAPPED | UC_HOOK_MEM_WRITE_UNMAPPED, self.hook_mem_invalid)
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self.mu.hook_add(UC_HOOK_MEM_FETCH_UNMAPPED, self.hook_mem_fetch_unmapped)
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def hook_mem_fetch_unmapped(self, uc, access, address, size, value, user_data):
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next_ip = self.unicorn_code + size
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self.write_reg(UC_X86_REG_RIP, next_ip)
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self.write_data(next_ip, b"\x90")
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# self.write_reg(UC_X86_REG_RIP, address) # ???
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return True
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def hook_mem_invalid(self, uc, access, address, size, value, user_data):
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regress.logger.debug("invalid mem access: access type = %d, to = %#x, size = %u, value = %#x", access, address,
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size, value)
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return True
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def hook_mem_access(self, uc, access, address, size, value, user_data):
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return True
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def emu(self, steps):
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ip = self.mu.reg_read(UC_X86_REG_RIP)
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max_intel_insn_size = 15
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regress.logger.debug("starting at : %#x", ip)
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self.mu.emu_start(ip, ip + max_intel_insn_size, count=steps)
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def write_data(self, address, content):
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self.mu.mem_write(address, content)
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def write_reg(self, reg, value):
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self.mu.reg_write(reg, value)
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class TranslatorBuffer(regress.RegressTest):
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def init_unicorn(self, ip, sp, magic):
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emu = Emulator(ip, sp)
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emu.write_data(ip, b"\xf4" * 8)
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emu.write_data(sp, struct.pack("<Q", magic))
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emu.emu(1)
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@unittest.skipIf(platform.machine().lower() == 'aarch64', reason='TO BE CHECKED!')
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def runTest(self):
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ip_base = 0x000fffff816a0000 # was: 0xffffffff816a0000
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sp_base = 0x000f88001b800000 # was: 0xffff88001b800000
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mg_base = 0x000f880026f02000 # was: 0xffff880026f02000
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ips = range(0x9000, 0xf000, 8)
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sps = range(0x0000, 0x6000, 8)
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for i, (ip, sp) in enumerate(zip(ips, sps)):
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self.init_unicorn(ip_base + ip, sp_base + sp, mg_base + i * 8)
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if __name__ == '__main__':
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regress.main()
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