9cfd5cfac3
- Added fullMode input in workflow_dispatch
- Take decision whether to build either in debug or release mode and if to build for all python versions according to the commit message patterns
- Set proper artifact names
- Removed not needed steps
- Compacted some steps in order to leverage more the matrix feature
- Bumped cibuildwheel action to 2.22.0
- Run actual regress tests in place of sample scripts
- Specify optional test install in pyproject.toml with proper requirements
- Derive package version from git tags
- Add GENERATORS env var support in setup.py to specify cmake generator and minor refactoring
- Minor cleanup/refactoring for the regress test suite
- Marked some regress tests with skipIf to skip them in case of old python versions
- Marked some failing regress tests to be checked with skipIf
70 lines
2.4 KiB
Python
Executable File
70 lines
2.4 KiB
Python
Executable File
import regress
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from unicorn import *
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from unicorn.x86_const import *
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binary1 = b'\xb8\x02\x00\x00\x00' # mov eax, 2
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binary2 = b'\xb8\x01\x00\x00\x00' # mov eax, 1
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class WrongRIP(regress.RegressTest):
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def test_step(self):
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mu = Uc(UC_ARCH_X86, UC_MODE_64)
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mu.mem_map(0, 2 * 1024 * 1024)
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# write machine code to be emulated to memory
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mu.mem_write(0, binary1 + binary2)
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# emu for maximum 1 instruction.
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mu.emu_start(0, 5, 0, 1)
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self.assertEqual(0x2, mu.reg_read(UC_X86_REG_RAX))
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self.assertEqual(0x5, mu.reg_read(UC_X86_REG_RIP))
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mu.emu_start(5, 10, 0, 1)
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self.assertEqual(0xa, mu.reg_read(UC_X86_REG_RIP))
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self.assertEqual(0x1, mu.reg_read(UC_X86_REG_RAX))
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def test_step2(self):
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mu = Uc(UC_ARCH_X86, UC_MODE_64)
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mu.mem_map(0, 2 * 1024 * 1024)
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# write machine code to be emulated to memory
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mu.mem_write(0, binary1 + binary2)
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# emu for maximum 1 instruction.
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mu.emu_start(0, 10, 0, 1)
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self.assertEqual(0x2, mu.reg_read(UC_X86_REG_RAX))
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self.assertEqual(0x5, mu.reg_read(UC_X86_REG_RIP))
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mu.emu_start(5, 10, 0, 1)
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self.assertEqual(0x1, mu.reg_read(UC_X86_REG_RAX))
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self.assertEqual(0xa, mu.reg_read(UC_X86_REG_RIP))
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def test_step3(self):
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bin3 = b'\x40\x01\xc1\x31\xf6' # inc eax; add ecx, eax; xor esi, esi
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mu = Uc(UC_ARCH_X86, UC_MODE_32)
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mu.mem_map(0, 2 * 1024 * 1024)
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# write machine code to be emulated to memory
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mu.mem_write(0, bin3)
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# emu for maximum 1 instruction.
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mu.emu_start(0, 10, 0, 1)
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self.assertEqual(0x1, mu.reg_read(UC_X86_REG_EAX))
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self.assertEqual(0x1, mu.reg_read(UC_X86_REG_EIP))
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def test_step_then_fin(self):
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bin4 = b'\x40\x01\xc1\x31\xf6\x90\x90\x90' # inc eax; add ecx, eax; xor esi, esi
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mu = Uc(UC_ARCH_X86, UC_MODE_32)
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mu.mem_map(0, 2 * 1024 * 1024)
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# write machine code to be emulated to memory
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mu.mem_write(0, bin4)
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# emu for maximum 1 instruction.
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mu.emu_start(0, len(binary1), 0, 1)
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self.assertEqual(0x1, mu.reg_read(UC_X86_REG_EAX))
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self.assertEqual(0x1, mu.reg_read(UC_X86_REG_EIP))
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# emu to the end
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mu.emu_start(1, len(bin4))
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self.assertEqual(0x1, mu.reg_read(UC_X86_REG_EAX))
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self.assertEqual(len(bin4), mu.reg_read(UC_X86_REG_EIP))
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if __name__ == '__main__':
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regress.main()
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