9cfd5cfac3
- Added fullMode input in workflow_dispatch
- Take decision whether to build either in debug or release mode and if to build for all python versions according to the commit message patterns
- Set proper artifact names
- Removed not needed steps
- Compacted some steps in order to leverage more the matrix feature
- Bumped cibuildwheel action to 2.22.0
- Run actual regress tests in place of sample scripts
- Specify optional test install in pyproject.toml with proper requirements
- Derive package version from git tags
- Add GENERATORS env var support in setup.py to specify cmake generator and minor refactoring
- Minor cleanup/refactoring for the regress test suite
- Marked some regress tests with skipIf to skip them in case of old python versions
- Marked some failing regress tests to be checked with skipIf
103 lines
3.6 KiB
Python
Executable File
103 lines
3.6 KiB
Python
Executable File
# Moshe Kravchik
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import binascii
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import regress
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from unicorn import *
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from unicorn.arm_const import *
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# enable VFP
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ENABLE_VFP_CODE = (
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b"\x4f\xf4\x70\x03" # 00000016 mov.w r3, #0xf00000
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b"\x01\xee\x50\x3f" # 0000001a mcr p15, #0x0, r3, c1, c0, #0x2
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b"\xbf\xf3\x6f\x8f" # 0000bfb6 isb sy
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b"\x4f\xf0\x80\x43" # 0000bfba mov.w r3, #0x40000000
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b"\xe8\xee\x10\x3a" # 0000bfbe vmsr fpexc, r3
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)
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VLD_CODE = b"\x21\xf9\x0f\x6a" # 0000002a vld1.8 {d6, d7}, [r1]
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VST_CODE = b"\x00\xf9\x0f\x6a" # 0000002e vst1.8 {d6, d7}, [r0]
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# memory address where emulation starts
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ADDRESS = 0x10000
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SCRATCH_ADDRESS = 0x1000
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class SIMDNotReadArm(regress.RegressTest):
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def runTest(self):
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code = ENABLE_VFP_CODE + VLD_CODE + VST_CODE
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regress.logger.debug("Emulate THUMB code")
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# Initialize emulator in thumb mode
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mu = Uc(UC_ARCH_ARM, UC_MODE_THUMB)
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# map 2MB memory for this emulation
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mu.mem_map(ADDRESS, 2 * 1024 * 1024)
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# write machine code to be emulated to memory
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mu.mem_write(ADDRESS, code)
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# map 10K scratch memory for this emulation
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mu.mem_map(SCRATCH_ADDRESS, 10 * 1024)
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# write dummy data to be emulated to memory
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mu.mem_write(SCRATCH_ADDRESS, b"\x01" * 64)
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# initialize machine registers
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for i in range(UC_ARM_REG_R0, UC_ARM_REG_R12):
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mu.reg_write(i, i - UC_ARM_REG_R0)
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mu.reg_write(UC_ARM_REG_R1, SCRATCH_ADDRESS)
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mu.reg_write(UC_ARM_REG_R0, SCRATCH_ADDRESS + 0x100)
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mu.reg_write(UC_ARM_REG_SP, 0x1234)
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mu.reg_write(UC_ARM_REG_D6, UC_ARM_REG_D6)
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mu.reg_write(UC_ARM_REG_D7, UC_ARM_REG_D7)
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regress.logger.debug(">>> Before emulation")
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regress.logger.debug("\tD6 = %#x", mu.reg_read(UC_ARM_REG_D6))
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regress.logger.debug("\tD7 = %#x", mu.reg_read(UC_ARM_REG_D7))
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for i in range(UC_ARM_REG_R0, UC_ARM_REG_R12):
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regress.logger.debug("\tR%d = %#x", (i - UC_ARM_REG_R0), mu.reg_read(i))
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addr = SCRATCH_ADDRESS
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data = mu.mem_read(addr, 100)
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regress.logger.debug("Memory at addr %#x: %s", addr, binascii.hexlify(data))
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addr = SCRATCH_ADDRESS + 0x100
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data = mu.mem_read(addr, 100)
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regress.logger.debug("Memory at addr %#x: %s", addr, binascii.hexlify(data))
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self.assertEqual(UC_ARM_REG_D6, mu.reg_read(UC_ARM_REG_D6))
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self.assertEqual(UC_ARM_REG_D7, mu.reg_read(UC_ARM_REG_D7))
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# emulate machine code in infinite time
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mu.emu_start(ADDRESS | 0b1, ADDRESS + len(code))
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# now print out some registers
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regress.logger.debug(">>> After emulation")
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regress.logger.debug(">>> SP = %#x", mu.reg_read(UC_ARM_REG_SP))
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regress.logger.debug(">>> PC = %#x", mu.reg_read(UC_ARM_REG_PC))
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for i in range(UC_ARM_REG_R0, UC_ARM_REG_R12):
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regress.logger.debug("\tR%d = %#x", (i - UC_ARM_REG_R0), mu.reg_read(i))
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regress.logger.debug("\tD6 = %#x", mu.reg_read(UC_ARM_REG_D6))
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regress.logger.debug("\tD7 = %#x", mu.reg_read(UC_ARM_REG_D7))
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addr = SCRATCH_ADDRESS
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data = mu.mem_read(addr, 100)
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regress.logger.debug("Memory at addr %#x: %s", addr, binascii.hexlify(data))
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addr = SCRATCH_ADDRESS + 0x100
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data = mu.mem_read(addr, 100)
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regress.logger.debug("Memory at addr %#x: %s", addr, binascii.hexlify(data))
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self.assertEqual(mu.reg_read(UC_ARM_REG_D6), 0x0101010101010101)
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self.assertEqual(mu.reg_read(UC_ARM_REG_D7), 0x0101010101010101)
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if __name__ == '__main__':
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regress.main()
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