9cfd5cfac3
- Added fullMode input in workflow_dispatch
- Take decision whether to build either in debug or release mode and if to build for all python versions according to the commit message patterns
- Set proper artifact names
- Removed not needed steps
- Compacted some steps in order to leverage more the matrix feature
- Bumped cibuildwheel action to 2.22.0
- Run actual regress tests in place of sample scripts
- Specify optional test install in pyproject.toml with proper requirements
- Derive package version from git tags
- Add GENERATORS env var support in setup.py to specify cmake generator and minor refactoring
- Minor cleanup/refactoring for the regress test suite
- Marked some regress tests with skipIf to skip them in case of old python versions
- Marked some failing regress tests to be checked with skipIf
110 lines
4.2 KiB
Python
Executable File
110 lines
4.2 KiB
Python
Executable File
import regress
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import sys
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import unittest
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from unicorn import *
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from unicorn.sparc_const import *
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PAGE_SIZE = 1 * 1024 * 1024
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CODE = (
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b"\x80\x00\x20\x01" # add %g0, 1, %g0
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b"\x82\x00\x60\x01" # add %g1, 1, %g1
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b"\x84\x00\xA0\x01" # add %g2, 1, %g2
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b"\x86\x00\xE0\x01" # add %g3, 1, %g3
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b"\x88\x01\x20\x01" # add %g4, 1, %g4
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b"\x8A\x01\x60\x01" # add %g5, 1, %g5
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b"\x8C\x01\xA0\x01" # add %g6, 1, %g6
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b"\x8E\x01\xE0\x01" # add %g7, 1, %g7
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b"\x90\x02\x20\x01" # add %o0, 1, %o0
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b"\x92\x02\x60\x01" # add %o1, 1, %o1
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b"\x94\x02\xA0\x01" # add %o2, 1, %o2
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b"\x96\x02\xE0\x01" # add %o3, 1, %o3
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b"\x98\x03\x20\x01" # add %o4, 1, %o4
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b"\x9A\x03\x60\x01" # add %o5, 1, %o5
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b"\x9C\x03\xA0\x01" # add %sp, 1, %sp
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b"\x9E\x03\xE0\x01" # add %o7, 1, %o7
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b"\xA0\x04\x20\x01" # add %l0, 1, %l0
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b"\xA2\x04\x60\x01" # add %l1, 1, %l1
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b"\xA4\x04\xA0\x01" # add %l2, 1, %l2
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b"\xA6\x04\xE0\x01" # add %l3, 1, %l3
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b"\xA8\x05\x20\x01" # add %l4, 1, %l4
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b"\xAA\x05\x60\x01" # add %l5, 1, %l5
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b"\xAC\x05\xA0\x01" # add %l6, 1, %l6
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b"\xAE\x05\xE0\x01" # add %l7, 1, %l7
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b"\xB0\x06\x20\x01" # add %i0, 1, %i0
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b"\xB2\x06\x60\x01" # add %i1, 1, %i1
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b"\xB4\x06\xA0\x01" # add %i2, 1, %i2
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b"\xB6\x06\xE0\x01" # add %i3, 1, %i3
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b"\xB8\x07\x20\x01" # add %i4, 1, %i4
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b"\xBA\x07\x60\x01" # add %i5, 1, %i5
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b"\xBC\x07\xA0\x01" # add %fp, 1, %fp
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b"\xBE\x07\xE0\x01" # add %i7, 1, %i7
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)
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BASE = 0x00000000
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def hook_code(uc, addr, size, ud):
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regress.logger.debug("executing at 0x%04x", uc.reg_read(UC_SPARC_REG_PC))
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class TestSparc32RegRead(regress.RegressTest):
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@unittest.skipIf(sys.version_info < (3, 7), reason="requires python3.7 or higher")
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def runTest(self):
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uc = Uc(UC_ARCH_SPARC, UC_MODE_SPARC32 | UC_MODE_BIG_ENDIAN)
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uc.reg_write(UC_SPARC_REG_SP, 100)
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uc.reg_write(UC_SPARC_REG_FP, 200)
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uc.mem_map(BASE, PAGE_SIZE)
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uc.mem_write(BASE, CODE)
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uc.hook_add(UC_HOOK_CODE, hook_code)
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uc.emu_start(BASE, len(CODE))
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self.assertEqual(0, uc.reg_read(UC_SPARC_REG_G0)) # G0 is always zero
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self.assertEqual(1, uc.reg_read(UC_SPARC_REG_G1))
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self.assertEqual(1, uc.reg_read(UC_SPARC_REG_G2))
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self.assertEqual(1, uc.reg_read(UC_SPARC_REG_G3))
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self.assertEqual(1, uc.reg_read(UC_SPARC_REG_G4))
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self.assertEqual(1, uc.reg_read(UC_SPARC_REG_G5))
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self.assertEqual(1, uc.reg_read(UC_SPARC_REG_G6))
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self.assertEqual(1, uc.reg_read(UC_SPARC_REG_G7))
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self.assertEqual(1, uc.reg_read(UC_SPARC_REG_O0))
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self.assertEqual(1, uc.reg_read(UC_SPARC_REG_O1))
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self.assertEqual(1, uc.reg_read(UC_SPARC_REG_O2))
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self.assertEqual(1, uc.reg_read(UC_SPARC_REG_O3))
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self.assertEqual(1, uc.reg_read(UC_SPARC_REG_O4))
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self.assertEqual(1, uc.reg_read(UC_SPARC_REG_O5))
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self.assertEqual(101, uc.reg_read(UC_SPARC_REG_O6))
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self.assertEqual(1, uc.reg_read(UC_SPARC_REG_O7))
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self.assertEqual(1, uc.reg_read(UC_SPARC_REG_L0))
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self.assertEqual(1, uc.reg_read(UC_SPARC_REG_L1))
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self.assertEqual(1, uc.reg_read(UC_SPARC_REG_L2))
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self.assertEqual(1, uc.reg_read(UC_SPARC_REG_L3))
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self.assertEqual(1, uc.reg_read(UC_SPARC_REG_L4))
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self.assertEqual(1, uc.reg_read(UC_SPARC_REG_L5))
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self.assertEqual(1, uc.reg_read(UC_SPARC_REG_L6))
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self.assertEqual(1, uc.reg_read(UC_SPARC_REG_L7))
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self.assertEqual(1, uc.reg_read(UC_SPARC_REG_I0))
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self.assertEqual(1, uc.reg_read(UC_SPARC_REG_I1))
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self.assertEqual(1, uc.reg_read(UC_SPARC_REG_I2))
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self.assertEqual(1, uc.reg_read(UC_SPARC_REG_I3))
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self.assertEqual(1, uc.reg_read(UC_SPARC_REG_I4))
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self.assertEqual(1, uc.reg_read(UC_SPARC_REG_I5))
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self.assertEqual(201, uc.reg_read(UC_SPARC_REG_I6))
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self.assertEqual(1, uc.reg_read(UC_SPARC_REG_I7))
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# BUG: PC seems to get reset to 4 when done executing
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self.assertEqual(4 * 32, uc.reg_read(UC_SPARC_REG_PC)) # make sure we executed all instructions
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self.assertEqual(101, uc.reg_read(UC_SPARC_REG_SP))
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self.assertEqual(201, uc.reg_read(UC_SPARC_REG_FP))
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if __name__ == '__main__':
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regress.main()
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