9cfd5cfac3
- Added fullMode input in workflow_dispatch
- Take decision whether to build either in debug or release mode and if to build for all python versions according to the commit message patterns
- Set proper artifact names
- Removed not needed steps
- Compacted some steps in order to leverage more the matrix feature
- Bumped cibuildwheel action to 2.22.0
- Run actual regress tests in place of sample scripts
- Specify optional test install in pyproject.toml with proper requirements
- Derive package version from git tags
- Add GENERATORS env var support in setup.py to specify cmake generator and minor refactoring
- Minor cleanup/refactoring for the regress test suite
- Marked some regress tests with skipIf to skip them in case of old python versions
- Marked some failing regress tests to be checked with skipIf
188 lines
7.6 KiB
Python
Executable File
188 lines
7.6 KiB
Python
Executable File
#
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# This test demonstrates emulation behavior within and across
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# basic blocks.
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import binascii
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import struct
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import regress
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from unicorn import *
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from unicorn.x86_const import *
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CODE = (
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b"\xb8\x00\x00\x00\x00" # 1000: mov eax,0x0
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b"\x40" # 1005: inc eax
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b"\x40" # 1006: inc eax
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b"\x68\x10\x10\x00\x00" # 1007: push 0x1010
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b"\xc3" # 100c: ret
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b"\xcc" # 100d: int3
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b"\xcc" # 100e: int3
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b"\xcc" # 100f: int3
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b"\xb8\x00\x00\x00\x00" # 1010: mov eax,0x0
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b"\x40" # 1015: inc eax
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b"\x40" # 1016: inc eax
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)
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def showpc(mu):
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regress.logger.debug("pc: 0x%x", mu.reg_read(UC_X86_REG_EIP))
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class RunAcrossBBTest(regress.RegressTest):
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def test_run_all(self):
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try:
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#######################################################################
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# emu SETUP
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#######################################################################
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regress.logger.debug("\n---- test: run_all ----")
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mu = Uc(UC_ARCH_X86, UC_MODE_32)
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def hook_code(uc, address, size, user_data):
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regress.logger.debug(">>> Tracing instruction at 0x%x, instruction size = %u", address, size)
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mu.hook_add(UC_HOOK_CODE, hook_code)
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# base of CODE
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mu.mem_map(0x1000, 0x1000)
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mu.mem_write(0x1000, CODE)
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# stack
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mu.mem_map(0x2000, 0x1000)
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mu.reg_write(UC_X86_REG_EIP, 0x1000)
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mu.reg_write(UC_X86_REG_ESP, 0x2800)
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self.assertEqual(0x1000, mu.reg_read(UC_X86_REG_EIP), "unexpected PC")
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self.assertEqual(0x2800, mu.reg_read(UC_X86_REG_ESP), "unexpected SP")
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showpc(mu)
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mu.emu_start(0x1000, 0x1016)
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# should exec the following four instructions:
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# 1000: b8 00 00 00 00 mov eax,0x0 <
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# 1005: 40 inc eax <
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# 1006: 40 inc eax <
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# 1007: 68 10 10 00 00 push 0x1010 <
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# 100c: c3 ret -----------+
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# 100d: cc int3 |
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# 100e: cc int3 |
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# 100f: cc int3 |
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# 1010: b8 00 00 00 00 mov eax,0x0 <-+
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# 1015: 40 inc eax <
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# 1016: 40 inc eax <
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self.assertEqual(0x1016, mu.reg_read(UC_X86_REG_EIP), "unexpected PC (2)")
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self.assertEqual(0x2800, mu.reg_read(UC_X86_REG_ESP), "unexpected SP (2)")
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showpc(mu)
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except UcError as e:
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eip = mu.reg_read(UC_X86_REG_EIP)
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if e.errno == UC_ERR_FETCH_UNMAPPED:
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# during initial test dev, bad fetch at 0x1010, but the data is there, and this proves it
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regress.logger.error("!!! about to bail due to bad fetch... here's the data at PC:")
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regress.logger.error(binascii.hexlify(mu.mem_read(eip, 8)))
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self.fail("ERROR: %s @ 0x%x" % (e, eip))
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def test_run_across_bb(self):
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try:
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#######################################################################
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# emu SETUP
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#######################################################################
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regress.logger.debug("\n---- test: run_across_bb ----")
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mu = Uc(UC_ARCH_X86, UC_MODE_32)
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def hook_code(uc, address, size, user_data):
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regress.logger.debug(">>> Tracing instruction at 0x%x, instruction size = %u", address, size)
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mu.hook_add(UC_HOOK_CODE, hook_code)
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# base of CODE
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mu.mem_map(0x1000, 0x1000)
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mu.mem_write(0x1000, CODE)
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# stack
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mu.mem_map(0x2000, 0x1000)
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mu.reg_write(UC_X86_REG_EIP, 0x1000)
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mu.reg_write(UC_X86_REG_ESP, 0x2800)
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self.assertEqual(0x1000, mu.reg_read(UC_X86_REG_EIP), "unexpected PC")
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self.assertEqual(0x2800, mu.reg_read(UC_X86_REG_ESP), "unexpected SP")
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showpc(mu)
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#######################################################################
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# emu_run ONE:
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# exectue four instructions, until the last instruction in a BB
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#######################################################################
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mu.emu_start(0x1000, 0x100c)
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# should exec the following four instructions:
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# 1000: b8 00 00 00 00 mov eax,0x0 <
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# 1005: 40 inc eax <
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# 1006: 40 inc eax <
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# 1007: 68 10 10 00 00 push 0x1010 <
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# should be at 0x100c, as requested
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self.assertEqual(0x100c, mu.reg_read(UC_X86_REG_EIP), "unexpected PC (2)")
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# single push, so stack diff is 0x4
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TOP_OF_STACK = 0x2800 - 0x4
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self.assertEqual(TOP_OF_STACK, mu.reg_read(UC_X86_REG_ESP), "unexpected SP (2)")
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# top of stack should be 0x1010
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self.assertEqual(0x1010,
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struct.unpack("<I", mu.mem_read(TOP_OF_STACK, 0x4))[0],
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"unexpected stack value")
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showpc(mu)
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#######################################################################
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# emu_run TWO
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# execute one instruction that jumps to a new BB
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#######################################################################
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mu.emu_start(0x100c, 0x1010)
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# should exec one instruction that jumps to 0x1010:
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# 100c: c3 ret -----------+
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# 100d: cc int3 |
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# 100e: cc int3 |
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# 100f: cc int3 |
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# 1010: b8 00 00 00 00 mov eax,0x0 <-+
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# should be at 0x1010, as requested
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self.assertEqual(0x1010, mu.reg_read(UC_X86_REG_EIP), "unexpected PC (3)")
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# single pop, so stack back at base
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self.assertEqual(0x2800, mu.reg_read(UC_X86_REG_ESP), "unexpected SP (3)")
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showpc(mu)
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#######################################################################
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# emu_run THREE
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# execute three instructions to verify things work as expected
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#######################################################################
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mu.emu_start(0x1010, 0x1016)
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# should exec the following three instructions:
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# 1010: b8 00 00 00 00 mov eax,0x0 <
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# 1015: 40 inc eax <
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# 1016: 40 inc eax <
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self.assertEqual(0x1016, mu.reg_read(UC_X86_REG_EIP),
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"unexpected PC (4): 0x%x vs 0x%x" % (0x1016, mu.reg_read(UC_X86_REG_EIP)))
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showpc(mu)
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except UcError as e:
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eip = mu.reg_read(UC_X86_REG_EIP)
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if e.errno == UC_ERR_FETCH_UNMAPPED:
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# during initial test dev, bad fetch at 0x1010, but the data is there, and this proves it
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regress.logger.error("!!! about to bail due to bad fetch... here's the data at PC:")
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regress.logger.error(binascii.hexlify(mu.mem_read(eip, 8)))
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self.fail("ERROR: %s @ 0x%x" % (e, eip))
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if __name__ == '__main__':
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regress.main()
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