Files
unicorn/tests/regress/mips_except.py
@Antelox 9cfd5cfac3 - Improved the GitHub python binding workflow: (#2072)
- Added fullMode input in workflow_dispatch
    - Take decision whether to build either in debug or release mode and if to build for all python versions according to the commit message patterns
    - Set proper artifact names
    - Removed not needed steps
    - Compacted some steps in order to leverage more the matrix feature
    - Bumped cibuildwheel action to 2.22.0
    - Run actual regress tests in place of sample scripts
- Specify optional test install in pyproject.toml with proper requirements
- Derive package version from git tags
- Add GENERATORS env var support in setup.py to specify cmake generator and minor refactoring
- Minor cleanup/refactoring for the regress test suite
- Marked some regress tests with skipIf to skip them in case of old python versions
- Marked some failing regress tests to be checked with skipIf
2024-12-29 22:24:48 +08:00

59 lines
1.6 KiB
Python
Executable File

import regress
import sys
import unittest
from unicorn import *
from unicorn.mips_const import *
CODE = (
b'\x00\x00\x00\x00' # nop
b'\x00\x00\xa4\x8f' # lw $a0, 0($sp)
)
BASE = 0x20000000
class MipsExcept(regress.RegressTest):
@unittest.skipIf(sys.version_info < (3, 7), reason="requires python3.7 or higher")
def runTest(self):
uc = Uc(UC_ARCH_MIPS, UC_MODE_MIPS32 + UC_MODE_LITTLE_ENDIAN)
uc.mem_map(BASE, 0x1000)
uc.mem_write(BASE, CODE)
# execute nop. we should be ok
uc.emu_start(BASE, BASE + len(CODE), count=1)
# ----------------------------------------
# set sp to a mapped but unaligned address to read from
uc.reg_write(UC_MIPS_REG_SP, BASE + 0x801)
with self.assertRaises(UcError) as m:
uc.emu_start(BASE + 4, BASE + len(CODE), count=1)
self.assertEqual(UC_ERR_READ_UNALIGNED, m.exception.errno)
# ----------------------------------------
# set sp to an umapped address to read from
uc.reg_write(UC_MIPS_REG_SP, 0xfffffff0)
with self.assertRaises(UcError) as m:
uc.emu_start(BASE + 4, BASE + len(CODE), count=1)
self.assertEqual(UC_ERR_READ_UNMAPPED, m.exception.errno)
# ----------------------------------------
uc.reg_write(UC_MIPS_REG_SP, 0x40000000)
with self.assertRaises(UcError) as m:
uc.emu_start(BASE + 4, BASE + len(CODE), count=1)
self.assertEqual(UC_ERR_READ_UNMAPPED, m.exception.errno)
if __name__ == '__main__':
regress.main()