9cfd5cfac3
- Added fullMode input in workflow_dispatch
- Take decision whether to build either in debug or release mode and if to build for all python versions according to the commit message patterns
- Set proper artifact names
- Removed not needed steps
- Compacted some steps in order to leverage more the matrix feature
- Bumped cibuildwheel action to 2.22.0
- Run actual regress tests in place of sample scripts
- Specify optional test install in pyproject.toml with proper requirements
- Derive package version from git tags
- Add GENERATORS env var support in setup.py to specify cmake generator and minor refactoring
- Minor cleanup/refactoring for the regress test suite
- Marked some regress tests with skipIf to skip them in case of old python versions
- Marked some failing regress tests to be checked with skipIf
87 lines
3.5 KiB
Python
Executable File
87 lines
3.5 KiB
Python
Executable File
import binascii
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import regress
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from unicorn import *
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from unicorn.x86_const import *
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# callback for tracing instructions
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def hook_code(uc, address, size, user_data):
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# invalid instruction?
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if size == 0xf1f1f1f1:
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return
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regress.logger.debug("[%#x] = %s", address, binascii.hexlify(uc.mem_read(address, size)))
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# callback for tracing Linux interrupt
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def hook_intr(uc, intno, user_data):
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# only handle Linux syscall
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rip = uc.reg_read(UC_X86_REG_RIP)
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regress.logger.debug("[%#x]: got interrupt %#x", rip, intno)
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regress.logger.debug(" EAX = %#010x", uc.reg_read(UC_X86_REG_EAX))
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regress.logger.debug(" EBX = %#010x", uc.reg_read(UC_X86_REG_EBX))
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regress.logger.debug(" ECX = %#010x", uc.reg_read(UC_X86_REG_ECX))
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regress.logger.debug(" EDX = %#010x", uc.reg_read(UC_X86_REG_EDX))
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uc.emu_stop()
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class Hang(regress.RegressTest):
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def runTest(self):
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# self modifying shellcode execve('/bin/sh')
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shellcode = (
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b'\xeb\x1c' # 00: jmp 0x1e
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b'\x5a' # 02: pop rdx
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b'\x89\xd6' # 03: mov esi, edx
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b'\x8b\x02' # 05: mov eax, [rdx]
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b'\x66\x3d\xca\x7d' # 07: cmp ax, 0x7dca
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b'\x75\x06' # 0b: jne 0x13
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b'\x66\x05\x03\x03' # 0d: add ax,0x303
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b'\x89\x02' # 11: mov [rdx], eax
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b'\xfe\xc2' # 13: inc dl
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b'\x3d\x41\x41\x41\x41' # 15: cmp eax, 0x41414141
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b'\x75\xe9' # 1a: jne 0x5
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b'\xff\xe6' # 1c: jmp rsi
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b'\xe8\xdf\xff\xff\xff' # 1e: call 0x2
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b'\x31\xd2' # 23: xor edx, edx
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b'\x6a\x0b' # 25: push 0xb
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b'\x58' # 27: pop rax
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b'\x99' # 28: cdq
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b'\x52' # 29: push rdx
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b'\x68\x2f\x2f\x73\x68' # 2a: push 0x68732f2f
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b'\x68\x2f\x62\x69\x6e' # 2f: push 0x6e69622f
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b'\x89\xe3' # 34: mov ebx, esp
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b'\x52' # 36: push rdx
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b'\x53' # 37: push rbx
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b'\x89\xe1' # 38: mov ecx, esp
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b'\xca\x7d\x41\x41\x41\x41\x41\x41\x41\x41' # 3a: .db ca 7d 41 41 41 41 41 41 41 41
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)
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address = 0x00000000
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mu = Uc(UC_ARCH_X86, UC_MODE_64)
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mu.mem_map(address, 0x1000)
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# tracing all instructions with customized callback
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mu.hook_add(UC_HOOK_CODE, hook_code)
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# handle interrupt ourself
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mu.hook_add(UC_HOOK_INTR, hook_intr)
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# setup stack
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mu.reg_write(UC_X86_REG_RSP, 0x1000 - 8)
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# write machine code to be emulated to memory
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mu.mem_write(address, shellcode)
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regress.logger.debug('Starting emulation')
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mu.emu_start(address, address + len(shellcode))
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if __name__ == '__main__':
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regress.main()
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