9cfd5cfac3
- Added fullMode input in workflow_dispatch
- Take decision whether to build either in debug or release mode and if to build for all python versions according to the commit message patterns
- Set proper artifact names
- Removed not needed steps
- Compacted some steps in order to leverage more the matrix feature
- Bumped cibuildwheel action to 2.22.0
- Run actual regress tests in place of sample scripts
- Specify optional test install in pyproject.toml with proper requirements
- Derive package version from git tags
- Add GENERATORS env var support in setup.py to specify cmake generator and minor refactoring
- Minor cleanup/refactoring for the regress test suite
- Marked some regress tests with skipIf to skip them in case of old python versions
- Marked some failing regress tests to be checked with skipIf
77 lines
2.9 KiB
Python
77 lines
2.9 KiB
Python
import regress
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import sys
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import unittest
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from unicorn import *
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from unicorn.arm_const import *
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SHELLCODE = (
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b'\x03\xF0\x8F\xE0' # 0001F894 ADD PC, PC, R3
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b'\x0D\x07\x21\xF4' # 0001F898 VLD1.8 {D0}, [R1]!
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b'\x0D\x07\x0C\xF4' # 0001F89C VST1.8 {D0}, [R12]!
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b'\x0D\x07\x21\xF4' # 0001F8A0 VLD1.8 {D0}, [R1]!
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b'\x0D\x07\x0C\xF4' # 0001F8A4 VST1.8 {D0}, [R12]!
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b'\x0D\x07\x21\xF4' # 0001F8A8 VLD1.8 {D0}, [R1]!
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b'\x0D\x07\x0C\xF4' # 0001F8AC VST1.8 {D0}, [R12]!
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b'\x0D\x07\x21\xF4' # 0001F8B0 VLD1.8 {D0}, [R1]!
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b'\x0D\x07\x0C\xF4' # 0001F8B4 VST1.8 {D0}, [R12]!
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b'\x0D\x07\x21\xF4' # 0001F8B8 VLD1.8 {D0}, [R1]!
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b'\x0D\x07\x0C\xF4' # 0001F8BC VST1.8 {D0}, [R12]!
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b'\x0D\x07\x21\xF4' # 0001F8C0 VLD1.8 {D0}, [R1]!
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b'\x0D\x07\x0C\xF4' # 0001F8C4 VST1.8 {D0}, [R12]!
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b'\x0D\x07\x21\xF4' # 0001F8C8 VLD1.8 {D0}, [R1]!
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b'\x0D\x07\x0C\xF4' # 0001F8CC VST1.8 {D0}, [R12]!
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b'\x04\x00\x12\xE3' # 0001F8D0 TST R2, #4
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b'\x04\x30\x91\x14' # 0001F8D4 LDRNE R3, [R1],#4
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b'\x04\x30\x8C\x14' # 0001F8D8 STRNE R3, [R12],#4
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b'\x82\x2F\xB0\xE1' # 0001F8DC MOVS R2, R2,LSL#31
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b'\xB2\x30\xD1\x20' # 0001F8E0 LDRHCS R3, [R1],#2
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b'\x00\x10\xD1\x15' # 0001F8E4 LDRBNE R1, [R1]
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b'\xB2\x30\xCC\x20' # 0001F8E8 STRHCS R3, [R12],#2
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b'\x00\x10\xCC\x15' # 0001F8EC STRBNE R1, [R12]
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)
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BASE = 0x1F894
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COPY_SRC = 0x1000
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COPY_DST = 0x2000
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COPY_LEN = 8
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DATA = b'c8' * COPY_LEN
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class ArmMemcpy(regress.RegressTest):
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@unittest.skipIf(sys.version_info < (3, 7), reason="requires python3.7 or higher")
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def test_arm_memcpy(self):
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uc = Uc(UC_ARCH_ARM, UC_MODE_ARM)
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uc.mem_map(COPY_SRC, 0x1000)
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uc.mem_map(COPY_DST, 0x1000)
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uc.mem_map(BASE & ~(0x1000 - 1), 0x1000)
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uc.mem_write(COPY_SRC, DATA)
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uc.mem_write(BASE, SHELLCODE)
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uc.reg_write_batch((
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(UC_ARM_REG_R12, COPY_DST),
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(UC_ARM_REG_R1, COPY_SRC),
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(UC_ARM_REG_R2, COPY_LEN),
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(UC_ARM_REG_R3, 0x24)
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))
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# enable_vfp
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# coproc=15, is64=0, sec=0, CRn=1, CRm=0, opc1=0, opc2=2
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CPACR = (15, 0, 0, 1, 0, 0, 2)
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cpacr = uc.reg_read(UC_ARM_REG_CP_REG, CPACR)
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uc.reg_write(UC_ARM_REG_CP_REG, CPACR + (cpacr | (0b11 << 20) | (0b11 << 22),))
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uc.reg_write(UC_ARM_REG_FPEXC, (0b1 << 30))
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uc.emu_start(BASE, BASE + len(SHELLCODE))
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src = uc.mem_read(COPY_SRC, len(DATA))
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dst = uc.mem_read(COPY_DST, len(DATA))
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self.assertEqual(DATA, src)
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self.assertEqual(DATA, dst)
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if __name__ == '__main__':
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regress.main()
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