139 lines
3.1 KiB
Zig
139 lines
3.1 KiB
Zig
// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
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pub const sparcConst = enum(c_int) {
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// SPARC32 CPU
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CPU_SPARC32_FUJITSU_MB86904 = 0,
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CPU_SPARC32_FUJITSU_MB86907 = 1,
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CPU_SPARC32_TI_MICROSPARC_I = 2,
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CPU_SPARC32_TI_MICROSPARC_II = 3,
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CPU_SPARC32_TI_MICROSPARC_IIEP = 4,
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CPU_SPARC32_TI_SUPERSPARC_40 = 5,
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CPU_SPARC32_TI_SUPERSPARC_50 = 6,
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CPU_SPARC32_TI_SUPERSPARC_51 = 7,
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CPU_SPARC32_TI_SUPERSPARC_60 = 8,
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CPU_SPARC32_TI_SUPERSPARC_61 = 9,
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CPU_SPARC32_TI_SUPERSPARC_II = 10,
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CPU_SPARC32_LEON2 = 11,
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CPU_SPARC32_LEON3 = 12,
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CPU_SPARC32_ENDING = 13,
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// SPARC64 CPU
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CPU_SPARC64_FUJITSU = 0,
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CPU_SPARC64_FUJITSU_III = 1,
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CPU_SPARC64_FUJITSU_IV = 2,
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CPU_SPARC64_FUJITSU_V = 3,
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CPU_SPARC64_TI_ULTRASPARC_I = 4,
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CPU_SPARC64_TI_ULTRASPARC_II = 5,
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CPU_SPARC64_TI_ULTRASPARC_III = 6,
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CPU_SPARC64_TI_ULTRASPARC_IIE = 7,
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CPU_SPARC64_SUN_ULTRASPARC_III = 8,
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CPU_SPARC64_SUN_ULTRASPARC_III_CU = 9,
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CPU_SPARC64_SUN_ULTRASPARC_IIII = 10,
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CPU_SPARC64_SUN_ULTRASPARC_IV = 11,
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CPU_SPARC64_SUN_ULTRASPARC_IV_PLUS = 12,
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CPU_SPARC64_SUN_ULTRASPARC_IIII_PLUS = 13,
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CPU_SPARC64_SUN_ULTRASPARC_T1 = 14,
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CPU_SPARC64_SUN_ULTRASPARC_T2 = 15,
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CPU_SPARC64_NEC_ULTRASPARC_I = 16,
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CPU_SPARC64_ENDING = 17,
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// SPARC registers
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SPARC_REG_INVALID = 0,
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SPARC_REG_F0 = 1,
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SPARC_REG_F1 = 2,
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SPARC_REG_F2 = 3,
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SPARC_REG_F3 = 4,
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SPARC_REG_F4 = 5,
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SPARC_REG_F5 = 6,
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SPARC_REG_F6 = 7,
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SPARC_REG_F7 = 8,
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SPARC_REG_F8 = 9,
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SPARC_REG_F9 = 10,
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SPARC_REG_F10 = 11,
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SPARC_REG_F11 = 12,
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SPARC_REG_F12 = 13,
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SPARC_REG_F13 = 14,
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SPARC_REG_F14 = 15,
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SPARC_REG_F15 = 16,
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SPARC_REG_F16 = 17,
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SPARC_REG_F17 = 18,
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SPARC_REG_F18 = 19,
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SPARC_REG_F19 = 20,
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SPARC_REG_F20 = 21,
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SPARC_REG_F21 = 22,
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SPARC_REG_F22 = 23,
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SPARC_REG_F23 = 24,
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SPARC_REG_F24 = 25,
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SPARC_REG_F25 = 26,
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SPARC_REG_F26 = 27,
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SPARC_REG_F27 = 28,
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SPARC_REG_F28 = 29,
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SPARC_REG_F29 = 30,
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SPARC_REG_F30 = 31,
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SPARC_REG_F31 = 32,
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SPARC_REG_F32 = 33,
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SPARC_REG_F34 = 34,
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SPARC_REG_F36 = 35,
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SPARC_REG_F38 = 36,
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SPARC_REG_F40 = 37,
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SPARC_REG_F42 = 38,
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SPARC_REG_F44 = 39,
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SPARC_REG_F46 = 40,
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SPARC_REG_F48 = 41,
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SPARC_REG_F50 = 42,
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SPARC_REG_F52 = 43,
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SPARC_REG_F54 = 44,
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SPARC_REG_F56 = 45,
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SPARC_REG_F58 = 46,
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SPARC_REG_F60 = 47,
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SPARC_REG_F62 = 48,
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SPARC_REG_FCC0 = 49,
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SPARC_REG_FCC1 = 50,
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SPARC_REG_FCC2 = 51,
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SPARC_REG_FCC3 = 52,
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SPARC_REG_G0 = 53,
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SPARC_REG_G1 = 54,
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SPARC_REG_G2 = 55,
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SPARC_REG_G3 = 56,
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SPARC_REG_G4 = 57,
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SPARC_REG_G5 = 58,
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SPARC_REG_G6 = 59,
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SPARC_REG_G7 = 60,
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SPARC_REG_I0 = 61,
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SPARC_REG_I1 = 62,
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SPARC_REG_I2 = 63,
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SPARC_REG_I3 = 64,
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SPARC_REG_I4 = 65,
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SPARC_REG_I5 = 66,
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SPARC_REG_FP = 67,
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SPARC_REG_I7 = 68,
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SPARC_REG_ICC = 69,
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SPARC_REG_L0 = 70,
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SPARC_REG_L1 = 71,
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SPARC_REG_L2 = 72,
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SPARC_REG_L3 = 73,
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SPARC_REG_L4 = 74,
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SPARC_REG_L5 = 75,
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SPARC_REG_L6 = 76,
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SPARC_REG_L7 = 77,
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SPARC_REG_O0 = 78,
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SPARC_REG_O1 = 79,
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SPARC_REG_O2 = 80,
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SPARC_REG_O3 = 81,
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SPARC_REG_O4 = 82,
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SPARC_REG_O5 = 83,
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SPARC_REG_SP = 84,
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SPARC_REG_O7 = 85,
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SPARC_REG_Y = 86,
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SPARC_REG_XCC = 87,
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SPARC_REG_PC = 88,
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SPARC_REG_ENDING = 89,
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SPARC_REG_O6 = 84,
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SPARC_REG_I6 = 67,
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};
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