mio
ffeddd7579
Some structs, specically CPUARMState is 16-bytes aligned. This causes segment fault because gcc tends to vectorize the assignment of the struct with infamous movaps tricks. Without this patch, we fail on manylinux with 2.17 glibc in release mode in i686. qemu_memalign will ensure the alignment across platforms.
566 lines
17 KiB
C
566 lines
17 KiB
C
/*
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* Sparc CPU init helpers
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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static void sparc_cpu_reset(CPUState *dev)
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{
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CPUState *s = CPU(dev);
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SPARCCPU *cpu = SPARC_CPU(s);
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SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(cpu);
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CPUSPARCState *env = &cpu->env;
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scc->parent_reset(dev);
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memset(env, 0, offsetof(CPUSPARCState, end_reset_fields));
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env->cwp = 0;
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#ifndef TARGET_SPARC64
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env->wim = 1;
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#endif
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env->regwptr = env->regbase + (env->cwp * 16);
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CC_OP = CC_OP_FLAGS;
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#if !defined(TARGET_SPARC64)
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env->psret = 0;
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env->psrs = 1;
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env->psrps = 1;
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#endif
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#ifdef TARGET_SPARC64
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env->pstate = PS_PRIV | PS_RED | PS_PEF;
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if (!cpu_has_hypervisor(env)) {
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env->pstate |= PS_AG;
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}
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env->hpstate = cpu_has_hypervisor(env) ? HS_PRIV : 0;
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env->tl = env->maxtl;
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env->gl = 2;
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cpu_tsptr(env)->tt = TT_POWER_ON_RESET;
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env->lsu = 0;
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#else
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env->mmuregs[0] &= ~(MMU_E | MMU_NF);
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env->mmuregs[0] |= env->def.mmu_bm;
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#endif
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env->pc = 0;
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env->npc = env->pc + 4;
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env->cache_control = 0;
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}
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static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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if (interrupt_request & CPU_INTERRUPT_HARD) {
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SPARCCPU *cpu = SPARC_CPU(cs);
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CPUSPARCState *env = &cpu->env;
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if (cpu_interrupts_enabled(env) && env->interrupt_index > 0) {
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int pil = env->interrupt_index & 0xf;
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int type = env->interrupt_index & 0xf0;
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if (type != TT_EXTINT || cpu_pil_allowed(env, pil)) {
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cs->exception_index = env->interrupt_index;
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sparc_cpu_do_interrupt(cs);
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return true;
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}
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}
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}
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return false;
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}
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void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
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{
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#if !defined(TARGET_SPARC64)
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env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
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#endif
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}
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static const sparc_def_t sparc_defs[] = {
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#ifdef TARGET_SPARC64
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{
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.name = "Fujitsu Sparc64",
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.iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 4,
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.maxtl = 4,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "Fujitsu Sparc64 III",
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.iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 5,
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.maxtl = 4,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "Fujitsu Sparc64 IV",
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.iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "Fujitsu Sparc64 V",
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.iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI UltraSparc I",
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.iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI UltraSparc II",
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.iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI UltraSparc IIi",
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.iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI UltraSparc IIe",
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.iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "Sun UltraSparc III",
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.iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "Sun UltraSparc III Cu",
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.iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_3,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "Sun UltraSparc IIIi",
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.iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "Sun UltraSparc IV",
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.iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_4,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "Sun UltraSparc IV+",
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.iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT,
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},
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{
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.name = "Sun UltraSparc IIIi+",
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.iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_3,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "Sun UltraSparc T1",
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/* defined in sparc_ifu_fdp.v and ctu.h */
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.iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_sun4v,
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.nwindows = 8,
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.maxtl = 6,
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.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
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| CPU_FEATURE_GL,
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},
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{
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.name = "Sun UltraSparc T2",
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/* defined in tlu_asi_ctl.v and n2_revid_cust.v */
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.iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_sun4v,
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.nwindows = 8,
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.maxtl = 6,
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.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
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| CPU_FEATURE_GL,
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},
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{
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.name = "NEC UltraSparc I",
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.iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
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.fpu_version = 0x00000000,
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.mmu_version = mmu_us_12,
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.nwindows = 8,
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.maxtl = 5,
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.features = CPU_DEFAULT_FEATURES,
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},
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#else
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{
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.name = "Fujitsu MB86904",
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.iu_version = 0x04 << 24, /* Impl 0, ver 4 */
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.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
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.mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
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.mmu_bm = 0x00004000,
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.mmu_ctpr_mask = 0x00ffffc0,
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.mmu_cxr_mask = 0x000000ff,
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.mmu_sfsr_mask = 0x00016fff,
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.mmu_trcr_mask = 0x00ffffff,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "Fujitsu MB86907",
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.iu_version = 0x05 << 24, /* Impl 0, ver 5 */
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.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
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.mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
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.mmu_bm = 0x00004000,
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.mmu_ctpr_mask = 0xffffffc0,
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.mmu_cxr_mask = 0x000000ff,
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.mmu_sfsr_mask = 0x00016fff,
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.mmu_trcr_mask = 0xffffffff,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI MicroSparc I",
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.iu_version = 0x41000000,
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.fpu_version = 4 << 17,
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.mmu_version = 0x41000000,
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.mmu_bm = 0x00004000,
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.mmu_ctpr_mask = 0x007ffff0,
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.mmu_cxr_mask = 0x0000003f,
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.mmu_sfsr_mask = 0x00016fff,
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.mmu_trcr_mask = 0x0000003f,
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.nwindows = 7,
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.features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL |
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CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT |
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CPU_FEATURE_FMUL,
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},
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{
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.name = "TI MicroSparc II",
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.iu_version = 0x42000000,
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.fpu_version = 4 << 17,
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.mmu_version = 0x02000000,
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.mmu_bm = 0x00004000,
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.mmu_ctpr_mask = 0x00ffffc0,
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.mmu_cxr_mask = 0x000000ff,
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.mmu_sfsr_mask = 0x00016fff,
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.mmu_trcr_mask = 0x00ffffff,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI MicroSparc IIep",
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.iu_version = 0x42000000,
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.fpu_version = 4 << 17,
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.mmu_version = 0x04000000,
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.mmu_bm = 0x00004000,
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.mmu_ctpr_mask = 0x00ffffc0,
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.mmu_cxr_mask = 0x000000ff,
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.mmu_sfsr_mask = 0x00016bff,
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.mmu_trcr_mask = 0x00ffffff,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI SuperSparc 40", /* STP1020NPGA */
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.iu_version = 0x41000000, /* SuperSPARC 2.x */
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.fpu_version = 0 << 17,
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.mmu_version = 0x00000800, /* SuperSPARC 2.x, no MXCC */
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.mmu_bm = 0x00002000,
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.mmu_ctpr_mask = 0xffffffc0,
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.mmu_cxr_mask = 0x0000ffff,
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.mmu_sfsr_mask = 0xffffffff,
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.mmu_trcr_mask = 0xffffffff,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI SuperSparc 50", /* STP1020PGA */
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.iu_version = 0x40000000, /* SuperSPARC 3.x */
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.fpu_version = 0 << 17,
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.mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
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.mmu_bm = 0x00002000,
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.mmu_ctpr_mask = 0xffffffc0,
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.mmu_cxr_mask = 0x0000ffff,
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.mmu_sfsr_mask = 0xffffffff,
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.mmu_trcr_mask = 0xffffffff,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI SuperSparc 51",
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.iu_version = 0x40000000, /* SuperSPARC 3.x */
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.fpu_version = 0 << 17,
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.mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
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.mmu_bm = 0x00002000,
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.mmu_ctpr_mask = 0xffffffc0,
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.mmu_cxr_mask = 0x0000ffff,
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.mmu_sfsr_mask = 0xffffffff,
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.mmu_trcr_mask = 0xffffffff,
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.mxcc_version = 0x00000104,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI SuperSparc 60", /* STP1020APGA */
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.iu_version = 0x40000000, /* SuperSPARC 3.x */
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.fpu_version = 0 << 17,
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.mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
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.mmu_bm = 0x00002000,
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.mmu_ctpr_mask = 0xffffffc0,
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.mmu_cxr_mask = 0x0000ffff,
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.mmu_sfsr_mask = 0xffffffff,
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.mmu_trcr_mask = 0xffffffff,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI SuperSparc 61",
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.iu_version = 0x44000000, /* SuperSPARC 3.x */
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.fpu_version = 0 << 17,
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.mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
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.mmu_bm = 0x00002000,
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.mmu_ctpr_mask = 0xffffffc0,
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.mmu_cxr_mask = 0x0000ffff,
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.mmu_sfsr_mask = 0xffffffff,
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.mmu_trcr_mask = 0xffffffff,
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.mxcc_version = 0x00000104,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "TI SuperSparc II",
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.iu_version = 0x40000000, /* SuperSPARC II 1.x */
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.fpu_version = 0 << 17,
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.mmu_version = 0x08000000, /* SuperSPARC II 1.x, MXCC */
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.mmu_bm = 0x00002000,
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.mmu_ctpr_mask = 0xffffffc0,
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.mmu_cxr_mask = 0x0000ffff,
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.mmu_sfsr_mask = 0xffffffff,
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.mmu_trcr_mask = 0xffffffff,
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.mxcc_version = 0x00000104,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES,
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},
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{
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.name = "LEON2",
|
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.iu_version = 0xf2000000,
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.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
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.mmu_version = 0xf2000000,
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.mmu_bm = 0x00004000,
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.mmu_ctpr_mask = 0x007ffff0,
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.mmu_cxr_mask = 0x0000003f,
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.mmu_sfsr_mask = 0xffffffff,
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.mmu_trcr_mask = 0xffffffff,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN,
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},
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{
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.name = "LEON3",
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.iu_version = 0xf3000000,
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.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
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.mmu_version = 0xf3000000,
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.mmu_bm = 0x00000000,
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.mmu_ctpr_mask = 0xfffffffc,
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.mmu_cxr_mask = 0x000000ff,
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.mmu_sfsr_mask = 0xffffffff,
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.mmu_trcr_mask = 0xffffffff,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN |
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CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL | CPU_FEATURE_POWERDOWN |
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CPU_FEATURE_CASA,
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},
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#endif
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};
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|
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static void sparc_cpu_set_pc(CPUState *cs, vaddr value)
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{
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SPARCCPU *cpu = SPARC_CPU(cs);
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cpu->env.pc = value;
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cpu->env.npc = value + 4;
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}
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|
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static void sparc_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
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{
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SPARCCPU *cpu = SPARC_CPU(cs);
|
|
|
|
cpu->env.pc = tb->pc;
|
|
cpu->env.npc = tb->cs_base;
|
|
}
|
|
|
|
static bool sparc_cpu_has_work(CPUState *cs)
|
|
{
|
|
SPARCCPU *cpu = SPARC_CPU(cs);
|
|
CPUSPARCState *env = &cpu->env;
|
|
|
|
return (cs->interrupt_request & CPU_INTERRUPT_HARD) &&
|
|
cpu_interrupts_enabled(env);
|
|
}
|
|
|
|
static void sparc_cpu_realizefn(struct uc_struct *uc, CPUState *dev)
|
|
{
|
|
CPUState *cs = CPU(dev);
|
|
SPARCCPU *cpu = SPARC_CPU(dev);
|
|
CPUSPARCState *env = &cpu->env;
|
|
|
|
env->version = env->def.iu_version;
|
|
env->fsr = env->def.fpu_version;
|
|
env->nwindows = env->def.nwindows;
|
|
#if !defined(TARGET_SPARC64)
|
|
env->mmuregs[0] |= env->def.mmu_version;
|
|
cpu_sparc_set_id(env, 0);
|
|
env->mxccregs[7] |= env->def.mxcc_version;
|
|
#else
|
|
env->mmu_version = env->def.mmu_version;
|
|
env->maxtl = env->def.maxtl;
|
|
env->version |= env->def.maxtl << 8;
|
|
env->version |= env->def.nwindows - 1;
|
|
#endif
|
|
|
|
cpu_exec_realizefn(cs);
|
|
}
|
|
|
|
static void sparc_cpu_initfn(struct uc_struct *uc, CPUState *obj)
|
|
{
|
|
SPARCCPU *cpu = SPARC_CPU(obj);
|
|
SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj);
|
|
CPUSPARCState *env = &cpu->env;
|
|
|
|
env->uc = uc;
|
|
|
|
cpu_set_cpustate_pointers(cpu);
|
|
|
|
if (scc->cpu_def) {
|
|
env->def = *scc->cpu_def;
|
|
}
|
|
}
|
|
|
|
static void sparc_cpu_class_init(struct uc_struct *uc, CPUClass *oc)
|
|
{
|
|
SPARCCPUClass *scc = SPARC_CPU_CLASS(oc);
|
|
CPUClass *cc = CPU_CLASS(oc);
|
|
|
|
/* parent class is CPUClass, parent_reset() is cpu_common_reset(). */
|
|
scc->parent_reset = cc->reset;
|
|
/* overwrite the CPUClass->reset to arch reset: x86_cpu_reset(). */
|
|
cc->reset = sparc_cpu_reset;
|
|
cc->has_work = sparc_cpu_has_work;
|
|
cc->do_interrupt = sparc_cpu_do_interrupt;
|
|
cc->cpu_exec_interrupt = sparc_cpu_exec_interrupt;
|
|
cc->set_pc = sparc_cpu_set_pc;
|
|
cc->synchronize_from_tb = sparc_cpu_synchronize_from_tb;
|
|
cc->tlb_fill_cpu = sparc_cpu_tlb_fill;
|
|
cc->do_unaligned_access = sparc_cpu_do_unaligned_access;
|
|
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
|
|
cc->tcg_initialize = sparc_tcg_init;
|
|
}
|
|
|
|
SPARCCPU *cpu_sparc_init(struct uc_struct *uc)
|
|
{
|
|
SPARCCPU *cpu;
|
|
CPUState *cs;
|
|
CPUClass *cc;
|
|
SPARCCPUClass *scc;
|
|
|
|
cpu = qemu_memalign(8, sizeof(*cpu));
|
|
if (cpu == NULL) {
|
|
return NULL;
|
|
}
|
|
memset((void*)cpu, 0, sizeof(*cpu));
|
|
|
|
if (uc->cpu_model == INT_MAX) {
|
|
#ifdef TARGET_SPARC64
|
|
uc->cpu_model = UC_CPU_SPARC64_SUN_ULTRASPARC_IV; // Sun UltraSparc IV
|
|
#else
|
|
uc->cpu_model = UC_CPU_SPARC32_LEON3; // Leon 3
|
|
#endif
|
|
} else if (uc->cpu_model >= ARRAY_SIZE(sparc_defs)) {
|
|
free(cpu);
|
|
return NULL;
|
|
}
|
|
|
|
cs = (CPUState *)cpu;
|
|
cc = (CPUClass *)&cpu->cc;
|
|
cs->cc = cc;
|
|
cs->uc = uc;
|
|
uc->cpu = cs;
|
|
|
|
/* init CPUClass */
|
|
cpu_class_init(uc, cc);
|
|
/* init SPARCCPUClass */
|
|
sparc_cpu_class_init(uc, cc);
|
|
/* init CPUState */
|
|
cpu_common_initfn(uc, cs);
|
|
/* init SPARC types scc->def */
|
|
scc = SPARC_CPU_CLASS(cc);
|
|
scc->cpu_def = &sparc_defs[uc->cpu_model];
|
|
|
|
/* init SPARCCPU */
|
|
sparc_cpu_initfn(uc, cs);
|
|
/* realize SPARCCPU */
|
|
sparc_cpu_realizefn(uc, cs);
|
|
/* realize CPUState */
|
|
|
|
// init address space
|
|
cpu_address_space_init(cs, 0, cs->memory);
|
|
|
|
qemu_init_vcpu(cs);
|
|
|
|
return cpu;
|
|
}
|