mio
ffeddd7579
Some structs, specically CPUARMState is 16-bytes aligned. This causes segment fault because gcc tends to vectorize the assignment of the struct with infamous movaps tricks. Without this patch, we fail on manylinux with 2.17 glibc in release mode in i686. qemu_memalign will ensure the alignment across platforms.
410 lines
11 KiB
C
410 lines
11 KiB
C
/*
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* QEMU RISC-V CPU
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*
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* Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
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* Copyright (c) 2017-2018 SiFive, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/ctype.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "fpu/softfloat-helpers.h"
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#include <uc_priv.h>
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/* RISC-V CPU definitions */
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// static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
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const char * const riscv_int_regnames[] = {
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"x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1",
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"x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3",
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"x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4",
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"x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
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"x28/t3", "x29/t4", "x30/t5", "x31/t6"
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};
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const char * const riscv_fpr_regnames[] = {
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"f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5",
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"f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1",
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"f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7",
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"f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7",
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"f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
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"f30/ft10", "f31/ft11"
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};
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static void set_misa(CPURISCVState *env, target_ulong misa)
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{
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env->misa_mask = env->misa = misa;
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}
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static void set_priv_version(CPURISCVState *env, int priv_ver)
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{
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env->priv_ver = priv_ver;
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}
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static void set_feature(CPURISCVState *env, int feature)
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{
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env->features |= (1ULL << feature);
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}
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static void set_resetvec(CPURISCVState *env, int resetvec)
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{
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env->resetvec = resetvec;
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}
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static void riscv_any_cpu_init(CPUState *obj)
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{
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CPURISCVState *env = &RISCV_CPU(obj)->env;
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set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
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set_priv_version(env, PRIV_VERSION_1_11_0);
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set_resetvec(env, DEFAULT_RSTVEC);
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}
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#if defined(TARGET_RISCV32)
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// rv32
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static void riscv_base32_cpu_init(CPUState *obj)
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{
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CPURISCVState *env = &RISCV_CPU(obj)->env;
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/* We set this in the realise function */
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set_misa(env, 0);
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}
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// sifive-u34
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static void rv32gcsu_priv1_10_0_cpu_init(CPUState *obj)
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{
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CPURISCVState *env = &RISCV_CPU(obj)->env;
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set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
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set_priv_version(env, PRIV_VERSION_1_10_0);
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set_resetvec(env, DEFAULT_RSTVEC);
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set_feature(env, RISCV_FEATURE_MMU);
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set_feature(env, RISCV_FEATURE_PMP);
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}
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// sifive-e31
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static void rv32imacu_nommu_cpu_init(CPUState *obj)
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{
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CPURISCVState *env = &RISCV_CPU(obj)->env;
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set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
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set_priv_version(env, PRIV_VERSION_1_10_0);
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set_resetvec(env, DEFAULT_RSTVEC);
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set_feature(env, RISCV_FEATURE_PMP);
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}
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#elif defined(TARGET_RISCV64)
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// rv64
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static void riscv_base64_cpu_init(CPUState *obj)
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{
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CPURISCVState *env = &RISCV_CPU(obj)->env;
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/* We set this in the realise function */
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set_misa(env, 0);
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}
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// sifive-u54
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static void rv64gcsu_priv1_10_0_cpu_init(CPUState *obj)
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{
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CPURISCVState *env = &RISCV_CPU(obj)->env;
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set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
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set_priv_version(env, PRIV_VERSION_1_10_0);
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set_resetvec(env, DEFAULT_RSTVEC);
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set_feature(env, RISCV_FEATURE_MMU);
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set_feature(env, RISCV_FEATURE_PMP);
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}
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// sifive-e51
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static void rv64imacu_nommu_cpu_init(CPUState *obj)
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{
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CPURISCVState *env = &RISCV_CPU(obj)->env;
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set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
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set_priv_version(env, PRIV_VERSION_1_10_0);
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set_resetvec(env, DEFAULT_RSTVEC);
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set_feature(env, RISCV_FEATURE_PMP);
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}
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#endif
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static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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env->pc = value;
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}
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static void riscv_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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env->pc = tb->pc;
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}
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static bool riscv_cpu_has_work(CPUState *cs)
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{
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RISCVCPU *cpu = RISCV_CPU(cs);
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CPURISCVState *env = &cpu->env;
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/*
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* Definition of the WFI instruction requires it to ignore the privilege
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* mode and delegation registers, but respect individual enables
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*/
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return (env->mip & env->mie) != 0;
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}
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void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
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target_ulong *data)
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{
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env->pc = data[0];
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}
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static void riscv_cpu_reset(CPUState *dev)
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{
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CPUState *cs = CPU(dev);
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RISCVCPU *cpu = RISCV_CPU(cs);
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RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
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CPURISCVState *env = &cpu->env;
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mcc->parent_reset(cs);
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env->priv = PRV_M;
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env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
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env->mcause = 0;
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env->pc = env->resetvec;
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cs->exception_index = EXCP_NONE;
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env->load_res = -1;
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set_default_nan_mode(1, &env->fp_status);
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}
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static void riscv_cpu_realize(struct uc_struct *uc, CPUState *dev)
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{
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CPUState *cs = CPU(dev);
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RISCVCPU *cpu = RISCV_CPU(dev);
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CPURISCVState *env = &cpu->env;
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int priv_version = PRIV_VERSION_1_11_0;
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target_ulong target_misa = 0;
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cpu_exec_realizefn(cs);
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if (cpu->cfg.priv_spec) {
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if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
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priv_version = PRIV_VERSION_1_11_0;
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} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
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priv_version = PRIV_VERSION_1_10_0;
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} else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.9.1")) {
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priv_version = PRIV_VERSION_1_09_1;
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} else {
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// error_setg(errp, "Unsupported privilege spec version '%s'", cpu->cfg.priv_spec);
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return;
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}
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}
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set_priv_version(env, priv_version);
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set_resetvec(env, DEFAULT_RSTVEC);
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if (cpu->cfg.mmu) {
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set_feature(env, RISCV_FEATURE_MMU);
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}
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if (cpu->cfg.pmp) {
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set_feature(env, RISCV_FEATURE_PMP);
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}
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/* If misa isn't set (rv32 and rv64 machines) set it here */
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if (!env->misa) {
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/* Do some ISA extension error checking */
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if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
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//error_setg(errp, "I and E extensions are incompatible");
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return;
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}
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if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
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// error_setg(errp, "Either I or E extension must be set");
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return;
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}
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if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
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cpu->cfg.ext_a & cpu->cfg.ext_f & cpu->cfg.ext_d)) {
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// warn_report("Setting G will also set IMAFD");
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cpu->cfg.ext_i = true;
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cpu->cfg.ext_m = true;
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cpu->cfg.ext_a = true;
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cpu->cfg.ext_f = true;
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cpu->cfg.ext_d = true;
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}
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/* Set the ISA extensions, checks should have happened above */
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if (cpu->cfg.ext_i) {
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target_misa |= RVI;
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}
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if (cpu->cfg.ext_e) {
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target_misa |= RVE;
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}
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if (cpu->cfg.ext_m) {
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target_misa |= RVM;
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}
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if (cpu->cfg.ext_a) {
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target_misa |= RVA;
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}
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if (cpu->cfg.ext_f) {
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target_misa |= RVF;
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}
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if (cpu->cfg.ext_d) {
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target_misa |= RVD;
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}
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if (cpu->cfg.ext_c) {
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target_misa |= RVC;
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}
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if (cpu->cfg.ext_s) {
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target_misa |= RVS;
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}
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if (cpu->cfg.ext_u) {
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target_misa |= RVU;
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}
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if (cpu->cfg.ext_h) {
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target_misa |= RVH;
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}
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set_misa(env, RVXLEN | target_misa);
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}
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cpu_reset(cs);
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}
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static void riscv_cpu_init(struct uc_struct *uc, CPUState *obj)
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{
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RISCVCPU *cpu = RISCV_CPU(obj);
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CPURISCVState *env = &cpu->env;
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// unicorn
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env->uc = uc;
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cpu_set_cpustate_pointers(cpu);
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}
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static void riscv_cpu_class_init(struct uc_struct *uc, CPUClass *c, void *data)
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{
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RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
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CPUClass *cc = CPU_CLASS(c);
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mcc->parent_reset = cc->reset;
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cc->reset = riscv_cpu_reset;
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cc->has_work = riscv_cpu_has_work;
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cc->do_interrupt = riscv_cpu_do_interrupt;
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cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt;
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cc->set_pc = riscv_cpu_set_pc;
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cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb;
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cc->do_unaligned_access = riscv_cpu_do_unaligned_access;
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cc->tcg_initialize = riscv_translate_init;
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cc->tlb_fill_cpu = riscv_cpu_tlb_fill;
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}
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typedef struct CPUModelInfo {
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const char *name;
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void (*initfn)(CPUState *obj);
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} CPUModelInfo;
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static const CPUModelInfo cpu_models[] = {
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{TYPE_RISCV_CPU_ANY, riscv_any_cpu_init},
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#ifdef TARGET_RISCV32
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{TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init},
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{TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init},
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{TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init},
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#endif
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#ifdef TARGET_RISCV64
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{TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init},
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{TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init},
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{TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init},
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#endif
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};
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RISCVCPU *cpu_riscv_init(struct uc_struct *uc)
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{
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RISCVCPU *cpu;
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CPUState *cs;
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CPUClass *cc;
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cpu = qemu_memalign(8, sizeof(*cpu));
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if (cpu == NULL) {
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return NULL;
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}
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memset((void*)cpu, 0, sizeof(*cpu));
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#ifdef TARGET_RISCV32
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if (uc->cpu_model == INT_MAX) {
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uc->cpu_model = UC_CPU_RISCV32_SIFIVE_U34;
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}
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#else
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/* TARGET_RISCV64 */
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if (uc->cpu_model == INT_MAX) {
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uc->cpu_model = UC_CPU_RISCV64_SIFIVE_U54;
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}
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#endif
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if (uc->cpu_model >= ARRAY_SIZE(cpu_models)) {
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free(cpu);
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return NULL;
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}
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cs = (CPUState *)cpu;
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cc = (CPUClass *)&cpu->cc;
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cs->cc = cc;
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cs->uc = uc;
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uc->cpu = (CPUState *)cpu;
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/* init CPUClass */
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cpu_class_init(uc, cc);
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/* init RISCVCPUClass */
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riscv_cpu_class_init(uc, cc, NULL);
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/* init device properties*/
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cpu->cfg.ext_i = true;
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cpu->cfg.ext_e = false;
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cpu->cfg.ext_g = true;
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cpu->cfg.ext_m = true;
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cpu->cfg.ext_a = true;
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cpu->cfg.ext_f = true;
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cpu->cfg.ext_d = true;
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cpu->cfg.ext_c = true;
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cpu->cfg.ext_s = true;
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cpu->cfg.ext_u = true;
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cpu->cfg.ext_h = false;
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cpu->cfg.ext_counters = true;
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cpu->cfg.ext_ifencei = true;
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cpu->cfg.ext_icsr = true;
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cpu->cfg.priv_spec = "v1.11.0";
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cpu->cfg.mmu = true;
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cpu->cfg.pmp = true;
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/* init CPUState */
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cpu_common_initfn(uc, cs);
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/* init CPU */
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riscv_cpu_init(uc, cs);
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/* init specific CPU model */
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cpu_models[uc->cpu_model].initfn(cs);
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/* realize CPU */
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riscv_cpu_realize(uc, cs);
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// init addresss space
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cpu_address_space_init(cs, 0, cs->memory);
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qemu_init_vcpu(cs);
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return cpu;
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}
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