9f578946d5
* Fix Python regression test suite (partial) * Fix Python regression test suite * Add a test for mapping at high addresses * Add ctl tests
46 lines
1.2 KiB
Python
Executable File
46 lines
1.2 KiB
Python
Executable File
#!/usr/bin/python
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import regress
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from unicorn import *
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from unicorn.x86_const import *
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from unicorn.arm_const import *
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CODE = (
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b'\x48\x31' # adds r1, #0x48
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b'\xff\x57' # ldrsb r7, [r7, r7]
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b'\x57\x5e' # ldrsh r7, [r2, r1]
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b'\x5a\x48' # ldr r0, [pc, #0x168]
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b'\xbf\x2f' # cmp r7, #0xbf
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b'\x2f\x62' # str r7, [r5, #0x20]
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b'\x69\x6e' # ldr r1, [r5, #0x64]
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b'\x2f\x73' # strb r7, [r5, #0xc]
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b'\x68\x48' # ldr r0, [pc, #0x1a0]
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b'\xc1\xef\x08\x57\x54\x5f\x6a\x3b\x58\x0f\x05' # data?
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)
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BASE = 0x00000000
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class WrongRIPArm(regress.RegressTest):
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def runTest(self):
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mu = Uc(UC_ARCH_ARM, UC_MODE_THUMB)
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mu.mem_map(BASE, 2 * 1024 * 1024)
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# write machine code to be emulated to memory
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mu.mem_write(BASE, CODE)
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mu.reg_write(UC_ARM_REG_R13, 1 * 1024 * 1024)
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# emu for maximum 1 instruction.
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mu.emu_start(BASE | 0b1, BASE + len(CODE), count=1)
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self.assertEqual(0x48, mu.reg_read(UC_ARM_REG_R1))
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self.assertEqual(0x2, mu.reg_read(UC_ARM_REG_R15))
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if __name__ == '__main__':
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regress.main()
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