9f578946d5
* Fix Python regression test suite (partial) * Fix Python regression test suite * Add a test for mapping at high addresses * Add ctl tests
63 lines
1.8 KiB
Python
Executable File
63 lines
1.8 KiB
Python
Executable File
#!/usr/bin/python
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import regress
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from unicorn import *
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from unicorn.x86_const import *
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from capstone import Cs, CS_ARCH_X86, CS_ARCH_X86, CS_MODE_64, CS_MODE_32
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CODE = (
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b'\xc7\x04\x24\x7f\x03\x00\x00' # mov DWORD PTR [rsp],0x37f
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b'\xd9\x2c\x24' # fldcw WORD PTR [rsp]
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b'\xd9\xd0' # fnop
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b'\xd9\x74\x24\x08' # fnstenv [rsp+0x8]
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b'\x59' # pop rcx
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)
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BASE = 0x00000000
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STACK = 0x00000f00
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def hook_code(uc, addr, size, user_data):
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cs = user_data
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data = uc.mem_read(addr, size)
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mnem, ops = next((insn.mnemonic, insn.op_str) for insn in cs.disasm(data, addr))
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regress.logger.debug("0x%x: %-12s %-24s", addr, mnem, ops)
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class FpuIP(regress.RegressTest):
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def test_32(self):
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mu = Uc(UC_ARCH_X86, UC_MODE_32)
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cs = Cs(CS_ARCH_X86, CS_MODE_32)
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mu.mem_map(BASE, 0x1000)
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mu.mem_write(BASE, CODE)
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mu.reg_write(UC_X86_REG_ESP, STACK)
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mu.hook_add(UC_HOOK_CODE, hook_code, cs)
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mu.emu_start(BASE, BASE + len(CODE), count=5)
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self.assertSequenceEqual(b'\x7f\x03\x00\x00\x00\x00\x00\x00', mu.mem_read(STACK + 8, 8))
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self.assertSequenceEqual(b'\x55\x55\x00\x00\x00\x00\x00\x00', mu.mem_read(STACK + 16, 8))
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def test_64(self):
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mu = Uc(UC_ARCH_X86, UC_MODE_64)
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cs = Cs(CS_ARCH_X86, CS_MODE_64)
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mu.mem_map(BASE, 0x1000)
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mu.mem_write(BASE, CODE)
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mu.reg_write(UC_X86_REG_RSP, STACK)
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mu.hook_add(UC_HOOK_CODE, hook_code, cs)
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mu.emu_start(BASE, BASE + len(CODE), count=5)
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self.assertSequenceEqual(b'\x7f\x03\x00\x00\x00\x00\x00\x00', mu.mem_read(STACK + 8, 8))
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self.assertSequenceEqual(b'\x55\x55\x00\x00\x00\x00\x00\x00', mu.mem_read(STACK + 16, 8))
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if __name__ == '__main__':
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regress.main()
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