9f578946d5
* Fix Python regression test suite (partial) * Fix Python regression test suite * Add a test for mapping at high addresses * Add ctl tests
106 lines
3.1 KiB
Python
Executable File
106 lines
3.1 KiB
Python
Executable File
#!/usr/bin/env python
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# Sample code for ARM of Unicorn. Nguyen Anh Quynh <aquynh@gmail.com>
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# Python sample ported by Loi Anh Tuan <loianhtuan@gmail.com>
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#
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import regress
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from unicorn import *
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from unicorn.arm_const import *
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# code to be emulated
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ARM_CODE = (
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b"\x37\x00\xa0\xe3" # mov r0, #0x37
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b"\x03\x10\x42\xe0" # sub r1, r2, r3
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)
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THUMB_CODE = b"\x83\xb0" # sub sp, #0xc
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# memory address where emulation starts
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ADDRESS = 0xF0000000
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# callback for tracing basic blocks
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def hook_block(uc, address, size, user_data):
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regress.logger.debug(">>> Tracing basic block at %#x, block size = %#x", address, size)
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# callback for tracing instructions
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def hook_code(uc, address, size, user_data):
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regress.logger.debug(">>> Tracing instruction at %#x, instruction size = %u", address, size)
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class TestInitInputCrash(regress.RegressTest):
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def test_arm(self):
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regress.logger.debug("Emulate ARM code")
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# Initialize emulator in ARM mode
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mu = Uc(UC_ARCH_ARM, UC_MODE_ARM)
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mem_size = 2 * (1024 * 1024)
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mu.mem_map(ADDRESS, mem_size)
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stack_address = ADDRESS + mem_size
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stack_size = stack_address # >>> here huge memory size
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mu.mem_map(stack_address, stack_size)
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# write machine code to be emulated to memory
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mu.mem_write(ADDRESS, ARM_CODE)
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# initialize machine registers
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mu.reg_write(UC_ARM_REG_R0, 0x1234)
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mu.reg_write(UC_ARM_REG_R2, 0x6789)
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mu.reg_write(UC_ARM_REG_R3, 0x3333)
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# tracing all basic blocks with customized callback
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mu.hook_add(UC_HOOK_BLOCK, hook_block)
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# tracing all instructions with customized callback
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mu.hook_add(UC_HOOK_CODE, hook_code)
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# emulate machine code in infinite time
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mu.emu_start(ADDRESS, ADDRESS + len(ARM_CODE))
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# now print out some registers
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regress.logger.debug(">>> Emulation done. Below is the CPU context")
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r0 = mu.reg_read(UC_ARM_REG_R0)
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r1 = mu.reg_read(UC_ARM_REG_R1)
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regress.logger.debug(">>> R0 = %#x", r0)
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regress.logger.debug(">>> R1 = %#x", r1)
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def test_thumb(self):
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regress.logger.debug("Emulate THUMB code")
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# Initialize emulator in thumb mode
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mu = Uc(UC_ARCH_ARM, UC_MODE_THUMB)
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# map 2MB memory for this emulation
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mu.mem_map(ADDRESS, 2 * 1024 * 1024)
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# write machine code to be emulated to memory
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mu.mem_write(ADDRESS, THUMB_CODE)
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# initialize machine registers
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mu.reg_write(UC_ARM_REG_SP, 0x1234)
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# tracing all basic blocks with customized callback
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mu.hook_add(UC_HOOK_BLOCK, hook_block)
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# tracing all instructions with customized callback
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mu.hook_add(UC_HOOK_CODE, hook_code)
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# emulate machine code in infinite time
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mu.emu_start(ADDRESS | 0b1, ADDRESS + len(THUMB_CODE))
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# now print out some registers
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regress.logger.debug(">>> Emulation done. Below is the CPU context")
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sp = mu.reg_read(UC_ARM_REG_SP)
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regress.logger.debug(">>> SP = %#x", sp)
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if __name__ == '__main__':
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regress.main()
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