9cfd5cfac3
- Added fullMode input in workflow_dispatch
- Take decision whether to build either in debug or release mode and if to build for all python versions according to the commit message patterns
- Set proper artifact names
- Removed not needed steps
- Compacted some steps in order to leverage more the matrix feature
- Bumped cibuildwheel action to 2.22.0
- Run actual regress tests in place of sample scripts
- Specify optional test install in pyproject.toml with proper requirements
- Derive package version from git tags
- Add GENERATORS env var support in setup.py to specify cmake generator and minor refactoring
- Minor cleanup/refactoring for the regress test suite
- Marked some regress tests with skipIf to skip them in case of old python versions
- Marked some failing regress tests to be checked with skipIf
68 lines
1.8 KiB
Python
Executable File
68 lines
1.8 KiB
Python
Executable File
#!/usr/bin/env python
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# Sample code for RISCV of Unicorn. Nguyen Anh Quynh <aquynh@gmail.com>
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from unicorn import *
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from unicorn.riscv_const import *
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'''
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$ cstool riscv64 1305100093850502
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0 13 05 10 00 addi a0, zero, 1
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4 93 85 05 02 addi a1, a1, 0x20
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'''
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RISCV_CODE = b"\x13\x05\x10\x00\x93\x85\x05\x02"
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# memory address where emulation starts
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ADDRESS = 0x10000
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# callback for tracing basic blocks
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def hook_block(uc, address, size, user_data):
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print(">>> Tracing basic block at 0x%x, block size = 0x%x" % (address, size))
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# callback for tracing instructions
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def hook_code(uc, address, size, user_data):
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print(">>> Tracing instruction at 0x%x, instruction size = 0x%x" % (address, size))
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# Test RISCV
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def test_riscv():
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print("Emulate RISCV code")
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try:
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# Initialize emulator in RISCV32 mode
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mu = Uc(UC_ARCH_RISCV, UC_MODE_RISCV32)
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# map 2MB memory for this emulation
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mu.mem_map(ADDRESS, 2 * 1024 * 1024)
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# write machine code to be emulated to memory
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mu.mem_write(ADDRESS, RISCV_CODE)
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# initialize machine registers
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mu.reg_write(UC_RISCV_REG_A0, 0x1234)
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mu.reg_write(UC_RISCV_REG_A1, 0x7890)
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# tracing all basic blocks with customized callback
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mu.hook_add(UC_HOOK_BLOCK, hook_block)
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# tracing all instructions with customized callback
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mu.hook_add(UC_HOOK_CODE, hook_code)
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# emulate machine code in infinite time
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mu.emu_start(ADDRESS, ADDRESS + len(RISCV_CODE))
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# now print out some registers
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print(">>> Emulation done. Below is the CPU context")
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a0 = mu.reg_read(UC_RISCV_REG_A0)
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a1 = mu.reg_read(UC_RISCV_REG_A1)
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print(">>> A0 = 0x%x" % a0)
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print(">>> A1 = 0x%x" % a1)
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except UcError as e:
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print("ERROR: %s" % e)
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if __name__ == '__main__':
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test_riscv()
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